From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id A10C12629 for ; Thu, 17 Jan 2019 15:11:24 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Jan 2019 06:11:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,489,1539673200"; d="scan'208";a="292325044" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga005.jf.intel.com with ESMTP; 17 Jan 2019 06:11:23 -0800 Received: from fmsmsx101.amr.corp.intel.com (10.18.124.199) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.408.0; Thu, 17 Jan 2019 06:11:22 -0800 Received: from fmsmsx108.amr.corp.intel.com ([169.254.9.99]) by fmsmsx101.amr.corp.intel.com ([169.254.1.125]) with mapi id 14.03.0415.000; Thu, 17 Jan 2019 06:11:22 -0800 From: "Eads, Gage" To: "Gavin Hu (Arm Technology China)" , "dev@dpdk.org" CC: "olivier.matz@6wind.com" , "arybchenko@solarflare.com" , "Richardson, Bruce" , "Ananyev, Konstantin" , Honnappa Nagarahalli , "Ruifeng Wang (Arm Technology China)" , "Phil Yang (Arm Technology China)" Thread-Topic: [dpdk-dev] [PATCH v2 2/2] mempool/nb_stack: add non-blocking stack mempool Thread-Index: AQHUrSJso0tnZem+LkyN190Zvz4vjKWzG7mggABlSRA= Date: Thu, 17 Jan 2019 14:11:22 +0000 Message-ID: <9184057F7FC11744A2107296B6B8EB1E541C83E4@FMSMSX108.amr.corp.intel.com> References: <20190110205538.24435-1-gage.eads@intel.com> <20190115223232.31866-1-gage.eads@intel.com> <20190115223232.31866-3-gage.eads@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMjc3ZjM0ZTQtZDk0OC00NjUyLWFkOTItODQxYjJlMDczNmUxIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoieEZPN2ZydDVtTkQwcUIxMTVremNod3VuWkgwQXlDc2V6aDdzUjEzWWh1ckdVbDlDNmNIdkZNZEdsNGVBamtlNyJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.1.200.108] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2 2/2] mempool/nb_stack: add non-blocking stack mempool X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Jan 2019 14:11:25 -0000 > -----Original Message----- > From: Gavin Hu (Arm Technology China) [mailto:Gavin.Hu@arm.com] > Sent: Thursday, January 17, 2019 2:06 AM > To: Eads, Gage ; dev@dpdk.org > Cc: olivier.matz@6wind.com; arybchenko@solarflare.com; Richardson, Bruce > ; Ananyev, Konstantin > ; Honnappa Nagarahalli > ; Ruifeng Wang (Arm Technology China) > ; Phil Yang (Arm Technology China) > > Subject: RE: [dpdk-dev] [PATCH v2 2/2] mempool/nb_stack: add non-blocking > stack mempool >=20 >=20 > > -----Original Message----- > > From: dev On Behalf Of Gage Eads > > Sent: Wednesday, January 16, 2019 6:33 AM > > To: dev@dpdk.org > > Cc: olivier.matz@6wind.com; arybchenko@solarflare.com; > > bruce.richardson@intel.com; konstantin.ananyev@intel.com > > Subject: [dpdk-dev] [PATCH v2 2/2] mempool/nb_stack: add non-blocking > > stack mempool > > > > This commit adds support for non-blocking (linked list based) stack > > mempool handler. The stack uses a 128-bit compare-and-swap > > instruction, and thus is limited to x86_64. The 128-bit CAS atomically > > updates the stack top pointer and a modification counter, which > > protects against the ABA problem. > > > > In mempool_perf_autotest the lock-based stack outperforms the non- > > blocking handler*, however: > > - For applications with preemptible pthreads, a lock-based stack's > > worst-case performance (i.e. one thread being preempted while > > holding the spinlock) is much worse than the non-blocking stack's. > > - Using per-thread mempool caches will largely mitigate the performance > > difference. > > > > *Test setup: x86_64 build with default config, dual-socket Xeon > > E5-2699 v4, running on isolcpus cores with a tickless scheduler. The > > lock-based stack's rate_persec was 1x-3.5x the non-blocking stack's. > > > > Signed-off-by: Gage Eads > > --- > > MAINTAINERS | 4 + > > config/common_base | 1 + > > doc/guides/prog_guide/env_abstraction_layer.rst | 5 + > > drivers/mempool/Makefile | 3 + > > drivers/mempool/meson.build | 5 + > > drivers/mempool/nb_stack/Makefile | 23 ++++ > > drivers/mempool/nb_stack/meson.build | 4 + > > drivers/mempool/nb_stack/nb_lifo.h | 147 > > +++++++++++++++++++++ > > drivers/mempool/nb_stack/rte_mempool_nb_stack.c | 125 > > ++++++++++++++++++ > > .../nb_stack/rte_mempool_nb_stack_version.map | 4 + > > mk/rte.app.mk | 7 +- > > 11 files changed, 326 insertions(+), 2 deletions(-) create mode > > 100644 drivers/mempool/nb_stack/Makefile create mode 100644 > > drivers/mempool/nb_stack/meson.build > > create mode 100644 drivers/mempool/nb_stack/nb_lifo.h > > create mode 100644 drivers/mempool/nb_stack/rte_mempool_nb_stack.c > > create mode 100644 > > drivers/mempool/nb_stack/rte_mempool_nb_stack_version.map > > > > diff --git a/MAINTAINERS b/MAINTAINERS index 470f36b9c..5519d3323 > > 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -416,6 +416,10 @@ M: Artem V. Andreev > > M: Andrew Rybchenko > > F: drivers/mempool/bucket/ > > > > +Non-blocking stack memory pool > > +M: Gage Eads > > +F: drivers/mempool/nb_stack/ > > + > > > > Bus Drivers > > ----------- > > diff --git a/config/common_base b/config/common_base index > > 964a6956e..8a51f36b1 100644 > > --- a/config/common_base > > +++ b/config/common_base > > @@ -726,6 +726,7 @@ CONFIG_RTE_LIBRTE_MEMPOOL_DEBUG=3Dn # > > CONFIG_RTE_DRIVER_MEMPOOL_BUCKET=3Dy > > CONFIG_RTE_DRIVER_MEMPOOL_BUCKET_SIZE_KB=3D64 > > +CONFIG_RTE_DRIVER_MEMPOOL_NB_STACK=3Dy >=20 > NAK, as this applies to x86_64 only, it will break arm/ppc and even 32bi= t i386 > configurations. >=20 Hi Gavin, This patch resolves that in the make and meson build files, which ensure th= at the library is only built for x86-64 targets: diff --git a/drivers/mempool/Makefile b/drivers/mempool/Makefile index 28c2e8360..895cf8a34 100644 --- a/drivers/mempool/Makefile +++ b/drivers/mempool/Makefile @@ -10,6 +10,9 @@ endif ifeq ($(CONFIG_RTE_EAL_VFIO)$(CONFIG_RTE_LIBRTE_FSLMC_BUS),yy) DIRS-$(CONFIG_RTE_LIBRTE_DPAA2_MEMPOOL) +=3D dpaa2 endif +ifeq ($(CONFIG_RTE_ARCH_X86_64),y) +DIRS-$(CONFIG_RTE_DRIVER_MEMPOOL_NB_STACK) +=3D nb_stack +endif diff --git a/drivers/mempool/nb_stack/meson.build b/drivers/mempool/nb_stac= k/meson.build new file mode 100644 index 000000000..4a699511d --- /dev/null +++ b/drivers/mempool/nb_stack/meson.build @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2019 Intel Corporation + +if arch_subdir !=3D 'x86' or cc.sizeof('void *') =3D=3D 4 + build =3D false +endif + +sources =3D files('rte_mempool_nb_stack.c') (Note: this code was pulled from the v3 patch) You can see successful 32-bit builds at the dpdk-test-report here: http://m= ails.dpdk.org/archives/test-report/2019-January/073636.html >=20 > IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended reci= pient, > please notify the sender immediately and do not disclose the contents to = any > other person, use it for any purpose, or store or copy the information in= any > medium. Thank you.