From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id 57A6010A3 for ; Thu, 17 Jan 2019 16:14:14 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Jan 2019 07:14:13 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,489,1539673200"; d="scan'208";a="110649176" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga008.jf.intel.com with ESMTP; 17 Jan 2019 07:14:13 -0800 Received: from fmsmsx118.amr.corp.intel.com (10.18.116.18) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.408.0; Thu, 17 Jan 2019 07:14:12 -0800 Received: from fmsmsx108.amr.corp.intel.com ([169.254.9.99]) by fmsmsx118.amr.corp.intel.com ([169.254.1.120]) with mapi id 14.03.0415.000; Thu, 17 Jan 2019 07:14:11 -0800 From: "Eads, Gage" To: "Gavin Hu (Arm Technology China)" , "dev@dpdk.org" CC: "olivier.matz@6wind.com" , "arybchenko@solarflare.com" , "Richardson, Bruce" , "Ananyev, Konstantin" , Honnappa Nagarahalli Thread-Topic: [dpdk-dev] [PATCH v2 1/2] eal: add 128-bit cmpset (x86-64 only) Thread-Index: AQHUrSJoKFD1BchWBki9OtDxKYLlAqWzIv3QgABwJWA= Date: Thu, 17 Jan 2019 15:14:11 +0000 Message-ID: <9184057F7FC11744A2107296B6B8EB1E541C84A3@FMSMSX108.amr.corp.intel.com> References: <20190110205538.24435-1-gage.eads@intel.com> <20190115223232.31866-1-gage.eads@intel.com> <20190115223232.31866-2-gage.eads@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNGY5ZTc1ODgtMTYwZS00NWZkLThhMTEtMDAwNjJhN2UxYjZhIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiUU9PK0RCS1NTQUNMWDUwQUQ0K013UDcwRFQ5R3Bkc3Qzb3JJenpRM3owaHhOc1FZekg4ano2STFPcGFIZnlpRSJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.1.200.108] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2 1/2] eal: add 128-bit cmpset (x86-64 only) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Jan 2019 15:14:14 -0000 > -----Original Message----- > From: Gavin Hu (Arm Technology China) [mailto:Gavin.Hu@arm.com] > Sent: Thursday, January 17, 2019 2:49 AM > To: Eads, Gage ; dev@dpdk.org > Cc: olivier.matz@6wind.com; arybchenko@solarflare.com; Richardson, Bruce > ; Ananyev, Konstantin > ; Honnappa Nagarahalli > > Subject: RE: [dpdk-dev] [PATCH v2 1/2] eal: add 128-bit cmpset (x86-64 on= ly) >=20 >=20 >=20 > > -----Original Message----- > > From: dev On Behalf Of Gage Eads > > Sent: Wednesday, January 16, 2019 6:33 AM > > To: dev@dpdk.org > > Cc: olivier.matz@6wind.com; arybchenko@solarflare.com; > > bruce.richardson@intel.com; konstantin.ananyev@intel.com > > Subject: [dpdk-dev] [PATCH v2 1/2] eal: add 128-bit cmpset (x86-64 > > only) > > > > This operation can be used for non-blocking algorithms, such as a > > non-blocking stack or ring. > > > > Signed-off-by: Gage Eads > > --- > > .../common/include/arch/x86/rte_atomic_64.h | 22 > > ++++++++++++++++++++++ > > 1 file changed, 22 insertions(+) > > > > diff --git a/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h > > b/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h > > index fd2ec9c53..34c2addf8 100644 > > --- a/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h > > +++ b/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h > > @@ -34,6 +34,7 @@ > > /* > > * Inspired from FreeBSD src/sys/amd64/include/atomic.h > > * Copyright (c) 1998 Doug Rabson > > + * Copyright (c) 2019 Intel Corporation > > * All rights reserved. > > */ > > > > @@ -208,4 +209,25 @@ static inline void > > rte_atomic64_clear(rte_atomic64_t *v) } #endif > > > > +static inline int > > +rte_atomic128_cmpset(volatile uint64_t *dst, uint64_t *exp, uint64_t > > *src) > > +{ > > +uint8_t res; > > + > > +asm volatile ( > > + MPLOCKED > > + "cmpxchg16b %[dst];" > > + " sete %[res]" > > + : [dst] "=3Dm" (*dst), > > +[res] "=3Dr" (res) > > + : "c" (src[1]), > > +"b" (src[0]), > > +"m" (*dst), > > +"d" (exp[1]), > > +"a" (exp[0]) > > + : "memory"); > > + > > +return res; > > +} > > + >=20 > CONFIG_RTE_DRIVER_MEMPOOL_NB_STACK=3Dy can't coexist with > RTE_FORCE_INTRINSICS=3Dy, this should be explicitly described somewhere i= n the > configuration and documentations. >=20 This patch places rte_atomic128_cmpset() outside of the RTE_FORCE_INTRINSIC= S ifndef, and this file is included regardless of that config flag, so it's= compiled either way. > > #endif /* _RTE_ATOMIC_X86_64_H_ */ > > -- > > 2.13.6 >=20 > IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended reci= pient, > please notify the sender immediately and do not disclose the contents to = any > other person, use it for any purpose, or store or copy the information in= any > medium. Thank you.