From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id A7E061B4E8 for ; Fri, 1 Feb 2019 18:11:06 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Feb 2019 09:11:05 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,549,1539673200"; d="scan'208";a="114548229" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga008.jf.intel.com with ESMTP; 01 Feb 2019 09:11:05 -0800 Received: from FMSMSX110.amr.corp.intel.com (10.18.116.10) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.408.0; Fri, 1 Feb 2019 09:11:05 -0800 Received: from fmsmsx108.amr.corp.intel.com ([169.254.9.99]) by FMSMSX110.amr.corp.intel.com ([169.254.14.203]) with mapi id 14.03.0415.000; Fri, 1 Feb 2019 09:11:04 -0800 From: "Eads, Gage" To: Honnappa Nagarahalli , "dev@dpdk.org" CC: "olivier.matz@6wind.com" , "arybchenko@solarflare.com" , "Richardson, Bruce" , "Ananyev, Konstantin" , "Gavin Hu (Arm Technology China)" , nd , "chaozhu@linux.vnet.ibm.com" , "jerinj@marvell.com" , "hemant.agrawal@nxp.com" , nd Thread-Topic: [PATCH 1/1] eal: add 128-bit cmpset (x86-64 only) Thread-Index: AQHUty75k/HjXbn82Ey1zVpEls/JgKXI2b8AgAJA/vA= Date: Fri, 1 Feb 2019 17:11:03 +0000 Message-ID: <9184057F7FC11744A2107296B6B8EB1E541CE21A@FMSMSX108.amr.corp.intel.com> References: <20190128172945.27251-1-gage.eads@intel.com> <20190128172945.27251-2-gage.eads@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNTZjOGYwNmEtYWRmMi00MGNkLWJjYzgtNWIzNDU5ZGE4Mzg2IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoieGpCV3d1ejQyY083MmNDend2czRqZ3BPR3hrTGlEOFVNWG1abWhlcXZINnBjNkduSEE5eHVabnhtQWlxVGh5aCJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.1.200.107] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH 1/1] eal: add 128-bit cmpset (x86-64 only) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Feb 2019 17:11:07 -0000 > -----Original Message----- > From: Honnappa Nagarahalli [mailto:Honnappa.Nagarahalli@arm.com] > Sent: Wednesday, January 30, 2019 11:48 PM > To: Eads, Gage ; dev@dpdk.org > Cc: olivier.matz@6wind.com; arybchenko@solarflare.com; Richardson, Bruce > ; Ananyev, Konstantin > ; Gavin Hu (Arm Technology China) > ; nd ; chaozhu@linux.vnet.ibm.com; > jerinj@marvell.com; hemant.agrawal@nxp.com; nd > Subject: RE: [PATCH 1/1] eal: add 128-bit cmpset (x86-64 only) >=20 > > > > This operation can be used for non-blocking algorithms, such as a non- > > blocking stack or ring. > > > > Signed-off-by: Gage Eads > > --- > > .../common/include/arch/x86/rte_atomic_64.h | 31 +++++++++++ > > lib/librte_eal/common/include/generic/rte_atomic.h | 65 > > ++++++++++++++++++++++ > > 2 files changed, 96 insertions(+) > > > > diff --git a/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h > > b/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h > > index fd2ec9c53..b7b90b83e 100644 > > --- a/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h > > +++ b/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h > > @@ -34,6 +34,7 @@ > > /* > > * Inspired from FreeBSD src/sys/amd64/include/atomic.h > > * Copyright (c) 1998 Doug Rabson > > + * Copyright (c) 2019 Intel Corporation > > * All rights reserved. > > */ > > > > @@ -46,6 +47,7 @@ > > > > #include > > #include > > +#include > > #include > > > > /*------------------------- 64 bit atomic operations > > -------------------------*/ @@ - > > 208,4 +210,33 @@ static inline void rte_atomic64_clear(rte_atomic64_t > > *v) } #endif > > > > +static inline int __rte_experimental > > +rte_atomic128_cmpset(volatile rte_int128_t *dst, > Does it make sense to call is rte_atomic128_compare_exchange (or > ..._cmp_xchg) to indicate it is a compare-exchange operation? >=20 Good point, though for v2 I'm planning to change this to true cmpset semant= ics (no update to exp on failure). See Ola's reply for the justification. > > + rte_int128_t *exp, rte_int128_t *src, > > + unsigned int weak, > > + enum rte_atomic_memmodel_t success, > > + enum rte_atomic_memmodel_t failure) { > > + RTE_SET_USED(weak); > > + RTE_SET_USED(success); > > + RTE_SET_USED(failure); > > + uint8_t res; > > + > > + asm volatile ( > > + MPLOCKED > > + "cmpxchg16b %[dst];" > > + " sete %[res]" > > + : [dst] "=3Dm" (dst->val[0]), > > + "=3DA" (exp->val[0]), > > + [res] "=3Dr" (res) > > + : "c" (src->val[1]), > > + "b" (src->val[0]), > > + "m" (dst->val[0]), > > + "d" (exp->val[1]), > > + "a" (exp->val[0]) > > + : "memory"); > > + > > + return res; > > +} > > + > > #endif /* _RTE_ATOMIC_X86_64_H_ */ > > diff --git a/lib/librte_eal/common/include/generic/rte_atomic.h > > b/lib/librte_eal/common/include/generic/rte_atomic.h > > index b99ba4688..8d612d566 100644 > > --- a/lib/librte_eal/common/include/generic/rte_atomic.h > > +++ b/lib/librte_eal/common/include/generic/rte_atomic.h > > @@ -14,6 +14,7 @@ > > > > #include > > #include > > +#include > > > > #ifdef __DOXYGEN__ > > > > @@ -1082,4 +1083,68 @@ static inline void > > rte_atomic64_clear(rte_atomic64_t *v) } #endif > > > > +/*------------------------ 128 bit atomic operations > > +-------------------------*/ > > + > > +/** > > + * 128-bit integer structure. > > + */ > > +typedef struct { > > + uint64_t val[2]; > > +} __rte_aligned(16) rte_int128_t; > It looks like '__int128' is available from gcc 4.6. I think we should use= '__int128'. > We can have it as an internal structure for ease of programming. >=20 Will add in v2. > > + > > +/** > > + * Memory consistency models used in atomic operations. These control > > +the > > + * behavior of the operation with respect to memory barriers and > > + * thread synchronization. > > + * > > + * These directly match those in the C++11 standard; for details on > > +their > > + * behavior, refer to the standard. > > + */ > > +enum rte_atomic_memmodel_t { > > + RTE_ATOMIC_RELAXED, > > + RTE_ATOMIC_CONSUME, > > + RTE_ATOMIC_ACQUIRE, > > + RTE_ATOMIC_RELEASE, > > + RTE_ATOMIC_ACQ_REL, > > + RTE_ATOMIC_SEQ_CST, > > +}; > IMO, we can use the GCC provided names. I do not see any advantage to > defining our own. >=20 Will change in v2. I was trying to avoid issues with GCC versions that don'= t have C++11 support, but DPDK's recommended minimum version (4.9) is later= than the version that added __atomic builtins (4.7). > > + > > +/* Only implemented on x86-64 currently. The ifdef prevents > > +compilation from > > + * failing for architectures without a definition of this function. > > + */ > Minor comment. We can skip the above comments, the #if below is pretty > obvious. >=20 Sure. Thanks, Gage