From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id AA9F12C17 for ; Mon, 4 Mar 2019 21:47:06 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Mar 2019 12:47:05 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,441,1544515200"; d="scan'208";a="279695779" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by orsmga004.jf.intel.com with ESMTP; 04 Mar 2019 12:47:05 -0800 Received: from fmsmsx157.amr.corp.intel.com (10.18.116.73) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.408.0; Mon, 4 Mar 2019 12:47:05 -0800 Received: from fmsmsx108.amr.corp.intel.com ([169.254.9.86]) by FMSMSX157.amr.corp.intel.com ([169.254.14.52]) with mapi id 14.03.0415.000; Mon, 4 Mar 2019 12:47:04 -0800 From: "Eads, Gage" To: Honnappa Nagarahalli , "dev@dpdk.org" CC: "olivier.matz@6wind.com" , "arybchenko@solarflare.com" , "Richardson, Bruce" , "Ananyev, Konstantin" , "Gavin Hu (Arm Technology China)" , nd , "chaozhu@linux.vnet.ibm.com" , "jerinj@marvell.com" , "hemant.agrawal@nxp.com" , nd Thread-Topic: [PATCH v2 1/1] eal: add 128-bit cmpxchg (x86-64 only) Thread-Index: AQHUysXakjH9lmVsC0GbLf2yDq3WuKX797FwgAAIy1A= Date: Mon, 4 Mar 2019 20:47:04 +0000 Message-ID: <9184057F7FC11744A2107296B6B8EB1E541F1710@FMSMSX108.amr.corp.intel.com> References: <20190128172945.27251-1-gage.eads@intel.com> <20190222154640.22029-1-gage.eads@intel.com> <20190222154640.22029-2-gage.eads@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMjhkODM5N2UtZWFiYy00NzUzLThjYWUtOGI4MGEwMzI3ZmJkIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoibW9MMUZDWVNPd2krTHYwUDFWalBYNGtoSTF0Y1pYeUE0K0N4T2pBWFhVN1FWZ3pKNHNQQytGT3A4dE9lbk9tayJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.1.200.107] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2 1/1] eal: add 128-bit cmpxchg (x86-64 only) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 04 Mar 2019 20:47:07 -0000 [snip] > > +/** > > + * An atomic compare and set function used by the mutex functions. > > + * (Atomically) Equivalent to: > > + * if (*dst =3D=3D exp) > Should be, "if (*dst =3D=3D *exp)" >=20 > > + * *dst =3D src > Should be "*dst =3D *src" >=20 Good catches, will fix both. > > + * else > > + * *exp =3D *dst > > + * > > + * @note The success and failure arguments must be one of the > > +__ATOMIC_* values > > + * defined in the C++11 standard. For details on their behavior, > > +refer to the > > + * standard. > > + * > > + * @param dst > > + * The destination into which the value will be written. > > + * @param exp > > + * Pointer to the expected value. If the operation fails, this memor= y is > > + * updated with the actual value. > > + * @param src > > + * Pointer to the new value. > > + * @param weak > > + * A value of true allows the comparison to spuriously fail and allo= ws the > > + * 'exp' update to occur non-atomically (i.e. a torn read may occur)= . > > + * Implementations may ignore this argument and only implement the > strong > > + * variant. > > + * @param success > > + * If successful, the operation's memory behavior conforms to this (= or a > > + * stronger) model. > > + * @param failure > > + * If unsuccessful, the operation's memory behavior conforms to this= (or a > > + * stronger) model. This argument cannot be __ATOMIC_RELEASE, > > + * __ATOMIC_ACQ_REL, or a stronger model than success. > > + * @return > > + * Non-zero on success; 0 on failure. > > + */ > > +static inline int __rte_experimental > > +rte_atomic128_cmpxchg(rte_int128_t *dst, > Name could be more neutral. May be rte_atomic128_compare/cmp_exchange? >=20 > > + rte_int128_t *exp, > > + const rte_int128_t *src, > > + unsigned int weak, > > + int success, > > + int failure); > > +#endif > > + > > #endif /* _RTE_ATOMIC_H_ */ > > -- > > 2.13.6 >=20 Sure -- I'll rename it rte_atomic128_cmp_exchange in the next version. > Few minor comments. > I have not reviewed the x86 implementation. > Otherwise, > Reviewed-by: Honnappa Nagarahalli Thanks, Gage