From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id DF8167CB6 for ; Mon, 25 Sep 2017 11:44:35 +0200 (CEST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Sep 2017 02:44:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,435,1500966000"; d="scan'208";a="139065661" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga002.jf.intel.com with ESMTP; 25 Sep 2017 02:44:34 -0700 Received: from fmsmsx117.amr.corp.intel.com (10.18.116.17) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 25 Sep 2017 02:44:34 -0700 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by fmsmsx117.amr.corp.intel.com (10.18.116.17) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 25 Sep 2017 02:44:33 -0700 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.159]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.213]) with mapi id 14.03.0319.002; Mon, 25 Sep 2017 17:44:32 +0800 From: "Xing, Beilei" To: "Rybalchenko, Kirill" , "dev@dpdk.org" CC: "Chilikin, Andrey" , "Wu, Jingjing" Thread-Topic: [PATCH v3 3/6] net/i40e: implement dynamic mapping of sw flow types to hw pctypes Thread-Index: AQHTMh10oRnkjcnZFEi5Hh1Ri2Nr6aLFWVdQ Date: Mon, 25 Sep 2017 09:44:31 +0000 Message-ID: <94479800C636CB44BD422CB454846E0132037325@SHSMSX101.ccr.corp.intel.com> References: <1504278166-32769-1-git-send-email-kirill.rybalchenko@intel.com> <1505917983-119112-1-git-send-email-kirill.rybalchenko@intel.com> <1505917983-119112-4-git-send-email-kirill.rybalchenko@intel.com> In-Reply-To: <1505917983-119112-4-git-send-email-kirill.rybalchenko@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v3 3/6] net/i40e: implement dynamic mapping of sw flow types to hw pctypes X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 25 Sep 2017 09:44:36 -0000 > -----Original Message----- > From: Rybalchenko, Kirill > Sent: Wednesday, September 20, 2017 10:33 PM > To: dev@dpdk.org > Cc: Rybalchenko, Kirill ; Chilikin, Andrey > ; Xing, Beilei ; Wu, > Jingjing > Subject: [PATCH v3 3/6] net/i40e: implement dynamic mapping of sw flow > types to hw pctypes >=20 > Implement dynamic mapping of software flow types to hardware pctypes. > This allows to add new flow types and pctypes for DDP without changing AP= I > of the driver. The mapping table is located in private data area for part= icular > network adapter and can be individually modified with set of appropriate > functions. >=20 > v2: > Re-arrange patchset to avoid compillation errors. > Remove usage of statically defined flow types and pctypes. >=20 > v3: > Changed prototypes of some static functions. > Fixed bugs in i40e_pctype_to_flowtype and i40e_flowtype_to_pctype > functions. > Various small modifications after reviewing. >=20 > Signed-off-by: Kirill Rybalchenko > --- > drivers/net/i40e/i40e_ethdev.c | 343 ++++++++++++--------------------= ------ > drivers/net/i40e/i40e_ethdev.h | 17 +- > drivers/net/i40e/i40e_ethdev_vf.c | 16 +- > drivers/net/i40e/i40e_fdir.c | 54 +++--- > drivers/net/i40e/i40e_flow.c | 5 +- > drivers/net/i40e/i40e_rxtx.c | 57 +++++++ > drivers/net/i40e/i40e_rxtx.h | 1 + > 7 files changed, 208 insertions(+), 285 deletions(-) >=20 > diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethde= v.c > index 18eac07..e396f73 100644 > --- a/drivers/net/i40e/i40e_ethdev.c > +++ b/drivers/net/i40e/i40e_ethdev.c >=20 > static int > -i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg) > +i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg, > + struct i40e_adapter *adapter) how about chaning the parameter order? i40e_hash_global_config_check(struct i40e_adapter *adapter, struct rte_eth_= hash_global_conf *g_cfg)? > { > uint32_t i; > - uint32_t mask0, i40e_mask =3D I40E_FLOW_TYPES; > + uint32_t mask0, i40e_mask =3D adapter->flow_types_mask; >=20 > if (g_cfg->hash_func !=3D RTE_ETH_HASH_FUNCTION_TOEPLITZ && > g_cfg->hash_func !=3D > RTE_ETH_HASH_FUNCTION_SIMPLE_XOR && @@ -7899,64 +7839,32 @@ > static int i40e_set_hash_filter_global_config(struct i40e_hw *hw, > struct rte_eth_hash_global_conf *g_cfg) { > + struct i40e_adapter *adapter =3D (struct i40e_adapter *)hw->back; > int ret; > - uint16_t i; > + uint16_t i, j; > uint32_t reg; > - uint32_t mask0 =3D g_cfg->valid_bit_mask[0]; > - enum i40e_filter_pctype pctype; > + /* > + * We work only with lowest 32 bits which is not correct, but to work > + * properly the valid_bit_mask size should be increased up to 64 bits > + * and this will brake ABI. This modification will be done in next > release > + */ > + uint32_t mask0 =3D g_cfg->valid_bit_mask[0] & > +(uint32_t)adapter->flow_types_mask; >=20 > /* Check the input parameters */ > - ret =3D i40e_hash_global_config_check(g_cfg); > + ret =3D i40e_hash_global_config_check(g_cfg, adapter); > if (ret < 0) > return ret; >=20 > - for (i =3D 0; mask0 && i < UINT32_BIT; i++) { > - if (!(mask0 & (1UL << i))) > - continue; > - mask0 &=3D ~(1UL << i); > - /* if flowtype is invalid, continue */ > - if (!I40E_VALID_FLOW(i)) > - continue; > - pctype =3D i40e_flowtype_to_pctype(i); > - reg =3D (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ? > - I40E_GLQF_HSYM_SYMH_ENA_MASK : 0; > - if (hw->mac.type =3D=3D I40E_MAC_X722) { > - if (pctype =3D=3D I40E_FILTER_PCTYPE_NONF_IPV4_UDP) > { > - reg); > - } else { > - i40e_write_rx_ctl(hw, > I40E_GLQF_HSYM(pctype), > - reg); > + for (i =3D RTE_ETH_FLOW_UNKNOWN + 1; i < UINT32_BIT; i++) { Should it be like following? for (i =3D RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT32_BIT; i++) { > + if (mask0 & (1UL << i)) { > + reg =3D (g_cfg->sym_hash_enable_mask[0] & (1UL << > i)) ? > + > I40E_GLQF_HSYM_SYMH_ENA_MASK : 0; > + > + for (j =3D I40E_FILTER_PCTYPE_INVALID + 1; > + j < I40E_FILTER_PCTYPE_MAX; j++) { > + if (adapter->pctypes_tbl[i] & (1ULL << j)) > + i40e_write_rx_ctl(hw, > I40E_GLQF_HSYM(j), reg); > } > - } else { > - i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), > reg); > } > } >=20 > @@ -8581,13 +8489,10 @@ i40e_filter_input_set_init(struct i40e_pf *pf) >=20 > for (pctype =3D I40E_FILTER_PCTYPE_NONF_IPV4_UDP; > pctype <=3D I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) { > - if (hw->mac.type =3D=3D I40E_MAC_X722) { > - if (!I40E_VALID_PCTYPE_X722(pctype)) > - continue; > - } else { > - if (!I40E_VALID_PCTYPE(pctype)) > - continue; > - } > + uint16_t flow_type =3D i40e_pctype_to_flowtype(pf->adapter, > pctype); Move the variable to the beginning of the function according to the code st= yle. > + > + if (flow_type =3D=3D RTE_ETH_FLOW_UNKNOWN) > + continue; >=20 > input_set =3D i40e_get_default_input_set(pctype); >=20 > @@ -8650,7 +8555,8 @@ i40e_hash_filter_inset_select(struct i40e_hw *hw, > return -EINVAL; > } >=20 > - if (!I40E_VALID_FLOW(conf->flow_type)) { > + pctype =3D i40e_flowtype_to_pctype(pf->adapter, conf->flow_type); > + if (pctype =3D=3D I40E_FILTER_PCTYPE_INVALID) { > PMD_DRV_LOG(ERR, "invalid flow_type input."); > return -EINVAL; > } > diff --git a/drivers/net/i40e/i40e_fdir.c b/drivers/net/i40e/i40e_fdir.c = index > 84c0a1f..810d384 100644 > --- a/drivers/net/i40e/i40e_fdir.c > +++ b/drivers/net/i40e/i40e_fdir.c > @@ -344,15 +344,10 @@ i40e_init_flx_pld(struct i40e_pf *pf) > /* initialize the masks */ > for (pctype =3D I40E_FILTER_PCTYPE_NONF_IPV4_UDP; > pctype <=3D I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) { > - if (hw->mac.type =3D=3D I40E_MAC_X722) { > - if (!I40E_VALID_PCTYPE_X722( > - (enum i40e_filter_pctype)pctype)) > - continue; > - } else { > - if (!I40E_VALID_PCTYPE( > - (enum i40e_filter_pctype)pctype)) > - continue; > - } > + uint16_t flow_type =3D i40e_pctype_to_flowtype(pf->adapter, > pctype); Same comments here, move 'uint16_t flow_type' to the beginning of the funct= ion. > + > + if (flow_type =3D=3D RTE_ETH_FLOW_UNKNOWN) > + continue; > pf->fdir.flex_mask[pctype].word_mask =3D 0; > i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0); > for (i =3D 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) { @@ - > 449,7 +444,8 @@ i40e_check_fdir_flex_payload(const struct > rte_eth_flex_payload_cfg *flex_cfg) > * arguments are valid > */ > static int > -i40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf) > +i40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf, > + const struct i40e_adapter *adapter) How about i40e_check_fdir_flex_conf(const struct i40e_adapter *adapter , co= nst struct rte_eth_fdir_flex_conf *conf)? > { > const struct rte_eth_flex_payload_cfg *flex_cfg; > const struct rte_eth_fdir_flex_mask *flex_mask; @@ -486,8 +482,11 > @@ i40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf) > return -EINVAL; > } > for (i =3D 0; i < conf->nb_flexmasks; i++) { > + enum i40e_filter_pctype pctype; Move the variable to the beginning of the function. > + > flex_mask =3D &conf->flex_mask[i]; > - if (!I40E_VALID_FLOW(flex_mask->flow_type)) { > + pctype =3D i40e_flowtype_to_pctype(adapter, flex_mask- > >flow_type); > + if (pctype =3D=3D I40E_FILTER_PCTYPE_INVALID) { > PMD_DRV_LOG(WARNING, "invalid flow type."); > return -EINVAL; > }