From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id 4ABCE1B204 for ; Thu, 12 Oct 2017 12:13:39 +0200 (CEST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Oct 2017 03:13:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.43,365,1503385200"; d="scan'208";a="909231728" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by FMSMGA003.fm.intel.com with ESMTP; 12 Oct 2017 03:13:38 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 12 Oct 2017 03:13:38 -0700 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.159]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.93]) with mapi id 14.03.0319.002; Thu, 12 Oct 2017 18:13:36 +0800 From: "Xing, Beilei" To: "Chilikin, Andrey" , "dev@dpdk.org" CC: "Wu, Jingjing" Thread-Topic: [PATCH] net/i40e: fix flexible payload configuration Thread-Index: AQHTPs6OARVBn9kEKU6HsSaXzs7GZaLgB7Yg Date: Thu, 12 Oct 2017 10:13:36 +0000 Message-ID: <94479800C636CB44BD422CB454846E013203EF27@SHSMSX101.ccr.corp.intel.com> References: <1507313486-9923-1-git-send-email-andrey.chilikin@intel.com> In-Reply-To: <1507313486-9923-1-git-send-email-andrey.chilikin@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] net/i40e: fix flexible payload configuration X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Oct 2017 10:13:39 -0000 > -----Original Message----- > From: Chilikin, Andrey > Sent: Saturday, October 7, 2017 2:11 AM > To: dev@dpdk.org > Cc: Xing, Beilei ; Wu, Jingjing > ; Chilikin, Andrey > Subject: [PATCH] net/i40e: fix flexible payload configuration >=20 > Removed legacy writes to ORT/PIT registers from i40e_GLQF_reg_init(struct > i40e_hw *hw) function. > Latest NVM versions contain all relevant values and these values should n= ot > be overwritten by SW to maintain driver/firmware compatibility and to avo= id > conflicts with dynamic device personalization profiles. >=20 > Signed-off-by: Andrey Chilikin > --- > drivers/net/i40e/i40e_ethdev.c | 23 +++++++++++------------ > 1 file changed, 11 insertions(+), 12 deletions(-) >=20 > diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethde= v.c > index e2af51c89..d770fc343 100644 > --- a/drivers/net/i40e/i40e_ethdev.c > +++ b/drivers/net/i40e/i40e_ethdev.c > @@ -704,23 +704,22 @@ RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* > igb_uio | uio_pci_generic | vfio-pci"); static inline void > i40e_GLQF_reg_init(struct i40e_hw *hw) { > /* > - * Initialize registers for flexible payload, which should be set by NV= M. > - * This should be removed from code once it is fixed in NVM. > + * Force global configuration for flexible payload > + * to the first 16 bytes of the corresponding L2/L3/L4 paylod. > + * This should be removed from code once proper > + * configuration API is added to avoid configuration conflicts > + * between ports of the same device. > */ > - I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030); > - I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030); > - I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B); > - I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B); > I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0); > I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3); > I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6); > - I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031); > - I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031); > - I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D); > - I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480); > - I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440); >=20 > - /* Initialize registers for parsing packet type of QinQ */ > + /* > + * Initialize registers for parsing packet type of QinQ > + * This should be removed from code once proper > + * configuration API is added to avoid configuration conflicts > + * between ports of the same device. > + */ > I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029); > I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420); } > -- > 2.13.0 Acked-by: Beilei Xing