From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id 5BD73C320 for ; Fri, 5 Jun 2015 17:12:16 +0200 (CEST) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP; 05 Jun 2015 08:12:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.13,559,1427785200"; d="scan'208";a="582747753" Received: from achabras-mobl2.ger.corp.intel.com ([10.252.49.200]) by orsmga003.jf.intel.com with ESMTP; 05 Jun 2015 08:12:13 -0700 Date: Fri, 5 Jun 2015 17:12:12 +0200 From: Roman Dementiev X-Priority: 3 (Normal) Message-ID: <95133134.20150605171212@intel.com> To: Stephen Hemminger In-Reply-To: <20150603114014.7f1fb67a@urahara> References: <1433250693-23644-1-git-send-email-roman.dementiev@intel.com> <20150603114014.7f1fb67a@urahara> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: "dev@dpdk.org" Subject: Re: [dpdk-dev] add support for HTM lock elision for x86 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 05 Jun 2015 15:12:16 -0000 Hello Stephen, Wednesday, June 3, 2015, 8:40:14 PM, you wrote: > On Tue, 2 Jun 2015 15:11:30 +0200 > Roman Dementiev wrote: >> >> This series of patches adds methods that use hardware memory transactions (HTM) >> on fast-path for DPDK locks (a.k.a. lock elision). Here the methods are implemented >> for x86 using Restricted Transactional Memory instructions (Intel(r) Transactional >> Synchronization Extensions). The implementation fall-backs to the normal DPDK lock >> if HTM is not available or memory transactions fail. >> This is not a replacement for all lock usages since not all critical sections protected >> by locks are friendly to HTM. >> > You probably want to put a caveat around this, it won't work for people > that expect to use spinlocks to protect I/O operations on hardware. > Since I/O operations aren't like memory. yes, I/O can not be rolled back by the CPU if the transaction should fail. Thus the HTM transaction protecting I/O operations are always aborted by CPU. In Intel TSX the I/O operations (MMIO, outp, etc) are TSX-unfriendly causing immediate abort. -- Best regards, Roman mailto:roman.dementiev@intel.com Intel GmbH Dornacher Strasse 1 85622 Feldkirchen/Muenchen, Deutschland Sitz der Gesellschaft: Feldkirchen bei Muenchen Geschaeftsfuehrer: Christian Lamprechter, Hannes Schwaderer, Douglas Lusk Registergericht: Muenchen HRB 47456 Ust.-IdNr./VAT Registration No.: DE129385895 Citibank Frankfurt a.M. (BLZ 502 109 00) 600119052