From: "Morten Brørup" <mb@smartsharesystems.com>
To: "Jan Viktorin" <viktorin@rehivetech.com>,
"Ruifeng Wang" <ruifeng.wang@arm.com>,
"David Christensen" <drc@linux.vnet.ibm.com>,
"Bruce Richardson" <bruce.richardson@intel.com>,
"Konstantin Ananyev" <konstantin.ananyev@intel.com>
Cc: <dev@dpdk.org>
Subject: rte_memcpy alignment
Date: Fri, 14 Jan 2022 09:56:50 +0100 [thread overview]
Message-ID: <98CBD80474FA8B44BF855DF32C47DC35D86E00@smartserver.smartshare.dk> (raw)
Dear ARM/POWER/x86 maintainers,
The architecture specific rte_memcpy() provides optimized variants to copy aligned data. However, the alignment requirements depend on the hardware architecture, and there is no common definition for the alignment.
DPDK provides __rte_cache_aligned for cache optimization purposes, with architecture specific values. Would you consider providing an __rte_memcpy_aligned for rte_memcpy() optimization purposes?
Or should I just use __rte_cache_aligned, although it is overkill?
Specifically, I am working on a mempool optimization where the objs field in the rte_mempool_cache structure may benefit by being aligned for optimized rte_memcpy().
Med venlig hilsen / Kind regards,
-Morten Brørup
next reply other threads:[~2022-01-14 8:56 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-14 8:56 Morten Brørup [this message]
2022-01-14 9:11 ` Bruce Richardson
2022-01-14 9:53 ` Morten Brørup
2022-01-14 10:22 ` Bruce Richardson
2022-01-14 10:54 ` Ananyev, Konstantin
2022-01-14 11:05 ` Morten Brørup
2022-01-14 11:51 ` Ananyev, Konstantin
2022-01-17 12:03 ` Morten Brørup
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