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Subject: RE: [RFC v2 3/7] ethdev: introduce Rx queue based limit watermark
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Date: Mon, 23 May 2022 08:07:44 +0200
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Thread-Topic: [RFC v2 3/7] ethdev: introduce Rx queue based limit watermark
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To: "Spike Du" <spiked@nvidia.com>, <matan@nvidia.com>,
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> From: Spike Du [mailto:spiked@nvidia.com]
> Sent: Sunday, 22 May 2022 07.59
>=20
> LWM(limit watermark) describes the fullness of a Rx queue. If the Rx
> queue fullness is above LWM, the device will trigger the event
> RTE_ETH_EVENT_RX_LWM.
> LWM is defined as a percentage of Rx queue size with valid value of
> [0,99].
> Setting LWM to 0 means disable it, which is the default.
> When translate the percentage to queue descriptor number, the numbe
> should be bigger than 0 and less than queue size.
> Add LWM's configuration and query driver callbacks in eth_dev_ops.
>=20
> Signed-off-by: Spike Du <spiked@nvidia.com>
> ---


> @@ -1249,7 +1249,16 @@ struct rte_eth_rxconf {
>  	 */
>  	union rte_eth_rxseg *rx_seg;
>=20
> -	uint64_t reserved_64s[2]; /**< Reserved for future fields */
> +	/**
> +	 * Per-queue Rx limit watermark defined as percentage of Rx queue
> +	 * size. If Rx queue receives traffic higher than this
> percentage,
> +	 * the event RTE_ETH_EVENT_RX_LWM is triggered.
> +	 */
> +	uint8_t lwm;

Why percentage, why not 1/128th, or 1/16th? 2^N seems more logical, and =
I wonder if such high granularity is really necessary. Just a thought, =
it's not important.

If you stick with percentage, it only needs 7 bits, and you can make the =
remaining one bit reserved.

Also, please add here that 0 means disable.

> +
> +	uint8_t reserved_bits[3];
> +	uint32_t reserved_32s;
> +	uint64_t reserved_64s;
>  	void *reserved_ptrs[2];   /**< Reserved for future fields */
>  };
>=20