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Subject: cache thrashing question
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Date: Fri, 25 Aug 2023 08:45:12 +0200
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From: =?iso-8859-1?Q?Morten_Br=F8rup?= <mb@smartsharesystems.com>
To: <bruce.richardson@intel.com>
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Bruce,

With this patch [1], it is noted that the ring producer and consumer =
data should not be on adjacent cache lines, for performance reasons.

[1]: =
https://git.dpdk.org/dpdk/commit/lib/librte_ring/rte_ring.h?id=3Dd9f0d3a1=
ffd4b66e75485cc8b63b9aedfbdfe8b0

(It's obvious that they cannot share the same cache line, because they =
are accessed by two different threads.)

Intuitively, I would think that having them on different cache lines =
would suffice. Why does having an empty cache line between them make a =
difference?

And does it need to be an empty cache line? Or does it suffice having =
the second structure start at two cache lines after the start of the =
first structure (e.g. if the size of the first structure is two cache =
lines)?

I'm asking because the same principle might apply to other code too.


Med venlig hilsen / Kind regards,
-Morten Br=F8rup