From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C114845501; Wed, 26 Jun 2024 14:01:52 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 55D6143424; Wed, 26 Jun 2024 13:56:10 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by mails.dpdk.org (Postfix) with ESMTP id 2971C42E95 for ; Wed, 26 Jun 2024 13:44:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719402282; x=1750938282; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7zDzMI81Pw+yRvpjtnD2E4a8922P8j2FXuJ+LDwfT1c=; b=lny0r+d2tQyJd5PVG6gCQvuDwYBeI2AkKQzzxpP2ayaEUhLTvWrLQE3w X35QfKihlPIVa2o3wU6zT5txR88X0c8ravv6stdwIKyMPrLmgoBDxwaDY DF9TflBkl4voeZxOCdLZVhnnx9+/5fyEZU3jXqtlDvBBvJhHJPUCKrsFt cROU8uU/yLc15Qd9Q8N2e6hEgPzZb6AOUUtYI3Xyr3LoYHiBRMUYdXttO 0nR3CmvOo5fTYVo9FBt8ci+TfUQYM3ez9gN2HdTDEUawsD41jKXKx/GKy Hrgywv1hlScZcEldfFxtNaU8V3imI9KksHuxEkRMHmJ4QibTf2MPsmZMx w==; X-CSE-ConnectionGUID: qonRNo47Q5KnvvPkcIV4FA== X-CSE-MsgGUID: JM64kMFmS7aVclSlOduSzA== X-IronPort-AV: E=McAfee;i="6700,10204,11114"; a="38979455" X-IronPort-AV: E=Sophos;i="6.08,266,1712646000"; d="scan'208";a="38979455" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jun 2024 04:44:41 -0700 X-CSE-ConnectionGUID: W7ap1fe4TNKsyUrD0FMMvw== X-CSE-MsgGUID: b225A9vmQXaIlBTszJUwfA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,266,1712646000"; d="scan'208";a="43874033" Received: from unknown (HELO silpixa00401119.ir.intel.com) ([10.55.129.167]) by orviesa010.jf.intel.com with ESMTP; 26 Jun 2024 04:44:41 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Karol Kolacinski , ian.stokes@intel.com, bruce.richardson@intel.com Subject: [PATCH v4 061/103] net/ice/base: add PHY OFFSET_READY register clearing Date: Wed, 26 Jun 2024 12:41:49 +0100 Message-ID: <99dff1e1ec1cf735652e5dd8734737136e413365.1719401848.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Karol Kolacinski Add a possibility to mark all transmitted/received timestamps as invalid by clearing PHY OFFSET_READY registers. Signed-off-by: Karol Kolacinski Signed-off-by: Ian Stokes --- drivers/net/ice/base/ice_ptp_hw.c | 84 +++++++++++++++++++++++++++++++ drivers/net/ice/base/ice_ptp_hw.h | 1 + 2 files changed, 85 insertions(+) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 0c8c339022..f78138ffb4 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -1903,6 +1903,38 @@ int ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port) return ice_write_phy_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 1); } +/** + * ice_ptp_clear_phy_offset_ready_eth56g - Clear PHY OFFSET_READY registers + * @hw: pointer to the HW struct + * + * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted + * and received timestamps as invalid. + */ +static int ice_ptp_clear_phy_offset_ready_eth56g(struct ice_hw *hw) +{ + u8 port; + + for (port = 0; port < hw->max_phy_port; port++) { + int err; + + err = ice_write_phy_reg_eth56g(hw, port, + PHY_REG_TX_OFFSET_READY, 0); + if (err) { + ice_warn(hw, "Failed to clear PHY TX_OFFSET_READY register\n"); + return err; + } + + err = ice_write_phy_reg_eth56g(hw, port, + PHY_REG_RX_OFFSET_READY, 0); + if (err) { + ice_warn(hw, "Failed to clear PHY RX_OFFSET_READY register\n"); + return err; + } + } + + return 0; +} + /** * ice_read_phy_and_phc_time_eth56g - Simultaneously capture PHC and PHY time * @hw: pointer to the HW struct @@ -3977,6 +4009,36 @@ int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port) return 0; } +/** + * ice_ptp_clear_phy_offset_ready_e822 - Clear PHY TX_/RX_OFFSET_READY registers + * @hw: pointer to the HW struct + * + * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted + * and received timestamps as invalid. + */ +static int ice_ptp_clear_phy_offset_ready_e822(struct ice_hw *hw) +{ + u8 port; + + for (port = 0; port < hw->phy_ports; port++) { + int err; + + err = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 0); + if (err) { + ice_warn(hw, "Failed to clear PHY TX_OFFSET_READY register\n"); + return err; + } + + err = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 0); + if (err) { + ice_warn(hw, "Failed to clear PHY RX_OFFSET_READY register\n"); + return err; + } + } + + return 0; +} + /** * ice_phy_cfg_fixed_rx_offset_e822 - Configure fixed Rx offset for bypass mode * @hw: pointer to the HW struct @@ -5721,6 +5783,28 @@ ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj) return ice_ptp_tmr_cmd(hw, ICE_PTP_ADJ_TIME_AT_TIME, true); } +/** + * ice_ptp_clear_phy_offset_ready - Clear PHY TX_/RX_OFFSET_READY registers + * @hw: pointer to the HW struct + * + * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted + * and received timestamps as invalid. + */ +int ice_ptp_clear_phy_offset_ready(struct ice_hw *hw) +{ + switch (hw->phy_cfg) { + case ICE_PHY_ETH56G: + return ice_ptp_clear_phy_offset_ready_eth56g(hw); + case ICE_PHY_E830: + case ICE_PHY_E810: + return 0; + case ICE_PHY_E822: + return ice_ptp_clear_phy_offset_ready_e822(hw); + default: + return ICE_ERR_NOT_SUPPORTED; + } +} + /** * ice_read_phy_tstamp - Read a PHY timestamp from the timestamp block * @hw: pointer to the HW struct diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index ff7719f16a..dfe5944b03 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -137,6 +137,7 @@ int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval); int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq); int ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj); +int ice_ptp_clear_phy_offset_ready(struct ice_hw *hw); int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp); int -- 2.43.0