From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id D72FC5A53 for ; Wed, 6 Jul 2016 07:39:08 +0200 (CEST) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP; 05 Jul 2016 22:38:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.28,317,1464678000"; d="scan'208";a="841281470" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga003.jf.intel.com with ESMTP; 05 Jul 2016 22:38:55 -0700 Received: from fmsmsx157.amr.corp.intel.com (10.18.116.73) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.248.2; Tue, 5 Jul 2016 22:38:55 -0700 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by FMSMSX157.amr.corp.intel.com (10.18.116.73) with Microsoft SMTP Server (TLS) id 14.3.248.2; Tue, 5 Jul 2016 22:38:54 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.181]) by shsmsx102.ccr.corp.intel.com ([169.254.2.147]) with mapi id 14.03.0248.002; Wed, 6 Jul 2016 13:38:53 +0800 From: "Wu, Jingjing" To: "Tao, Zhe" , "dev@dpdk.org" CC: "Tao, Zhe" Thread-Topic: [dpdk-dev] [PATCH v1] i40: fix the VXLAN TSO issue Thread-Index: AQHR1wA3FfE4l3cbskiMnI4A0v0WsKAK4VwQ Date: Wed, 6 Jul 2016 05:38:53 +0000 Message-ID: <9BB6961774997848B5B42BEC655768F80E167DF1@SHSMSX103.ccr.corp.intel.com> References: <1467752375-25984-1-git-send-email-zhe.tao@intel.com> In-Reply-To: <1467752375-25984-1-git-send-email-zhe.tao@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v1] i40: fix the VXLAN TSO issue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jul 2016 05:39:09 -0000 > --- a/drivers/net/i40e/i40e_rxtx.c > +++ b/drivers/net/i40e/i40e_rxtx.c > @@ -801,6 +801,12 @@ i40e_txd_enable_checksum(uint64_t ol_flags, > union i40e_tx_offload tx_offload, > uint32_t *cd_tunneling) > { > + /* Tx pkts tunnel type*/ > + if ((ol_flags & PKT_TX_TUNNEL_MASK) =3D=3D PKT_TX_TUNNEL_VXLAN) > + *cd_tunneling |=3D I40E_TXD_CTX_UDP_TUNNELING; > + else if ((ol_flags & PKT_TX_TUNNEL_MASK) =3D=3D > PKT_TX_TUNNEL_GRE) > + *cd_tunneling |=3D I40E_TXD_CTX_GRE_TUNNELING; > + > /* UDP tunneling packet TX checksum offload */ > if (ol_flags & PKT_TX_OUTER_IP_CKSUM) { >=20 Besides the tunnel type programming, please also check the L4TUNLEN in tunn= el parameters. > @@ -1510,7 +1516,8 @@ i40e_calc_context_desc(uint64_t flags) >=20 > /* set i40e TSO context descriptor */ > static inline uint64_t > -i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload= ) > +i40e_set_tso_ctx(struct rte_mbuf *mbuf, > + union i40e_tx_offload tx_offload) > { > uint64_t ctx_desc =3D 0; > uint32_t cd_cmd, hdr_len, cd_tso_len; > @@ -1537,7 +1544,6 @@ i40e_set_tso_ctx(struct rte_mbuf *mbuf, union > i40e_tx_offload tx_offload) Please have a look at the calculation of tso length here. Only tunnel type = added may not be enogh. =20 > I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) | > ((uint64_t)mbuf->tso_segsz << > I40E_TXD_CTX_QW1_MSS_SHIFT); > - > return ctx_desc; > } >=20 This patch contains changes on testpmd, driver and mbuf definition. It's be= tter to split them and sent to the maintainers.