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From: "Wu, Jingjing" <jingjing.wu@intel.com>
To: "Xing, Beilei" <beilei.xing@intel.com>
CC: "dev@dpdk.org" <dev@dpdk.org>
Thread-Topic: [PATCH] net/i40e: fix parsing QinQ packets type issue
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Date: Sun, 21 Aug 2016 01:21:19 +0000
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Subject: Re: [dpdk-dev] [PATCH] net/i40e: fix parsing QinQ packets type issue
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> -----Original Message-----
> From: Xing, Beilei
> Sent: Friday, August 19, 2016 11:20 AM
> To: Wu, Jingjing <jingjing.wu@intel.com>
> Cc: dev@dpdk.org; Xing, Beilei <beilei.xing@intel.com>
> Subject: [PATCH] net/i40e: fix parsing QinQ packets type issue
>=20
> Previously, PTYPE filed in the RX descriptors is not set properly
> for QinQ packets, wrong PTYPE is generated because outer Tag did
> not have ORT/PIT configured.
> Fix this issue by configuring ORT/PIT.
>=20
> Fixes: 4861cde46116 ("i40e: new poll mode driver")
>=20
> Signed-off-by: Beilei Xing <beilei.xing@intel.com>
> ---
> drivers/net/i40e/i40e_ethdev.c | 2 ++
> 1 file changed, 2 insertions(+)
>=20
> diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethde=
v.c
> index 55c4887..ba0eca0 100644
> --- a/drivers/net/i40e/i40e_ethdev.c
> +++ b/drivers/net/i40e/i40e_ethdev.c
> @@ -747,8 +747,10 @@ static inline void i40e_flex_payload_reg_init(struct=
i40e_hw *hw)
> I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
> I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
> I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
> + I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
Setting of GLQF_ORT(40) and GLQF_PIT(16) is for outer vlan, but not for Fle=
xible payload.
So it may not be suitable to put the code in i40e_flex_payload_reg_init.
How about change the function's name and add comments in code?
> /* GLQF_PIT Registers */
> + I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
> I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
> I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
> }
> --
> 2.5.0