* [dpdk-dev] [PATCH] net/i40e: fix parsing QinQ packets type issue @ 2016-08-19 3:20 Beilei Xing 2016-08-21 1:21 ` Wu, Jingjing 2016-08-23 9:44 ` [dpdk-dev] [PATCH v2] " Beilei Xing 0 siblings, 2 replies; 7+ messages in thread From: Beilei Xing @ 2016-08-19 3:20 UTC (permalink / raw) To: jingjing.wu; +Cc: dev, Beilei Xing Previously, PTYPE filed in the RX descriptors is not set properly for QinQ packets, wrong PTYPE is generated because outer Tag did not have ORT/PIT configured. Fix this issue by configuring ORT/PIT. Fixes: 4861cde46116 ("i40e: new poll mode driver") Signed-off-by: Beilei Xing <beilei.xing@intel.com> --- drivers/net/i40e/i40e_ethdev.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 55c4887..ba0eca0 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -747,8 +747,10 @@ static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw) I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031); I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031); I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D); + I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029); /* GLQF_PIT Registers */ + I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420); I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480); I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440); } -- 2.5.0 ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [dpdk-dev] [PATCH] net/i40e: fix parsing QinQ packets type issue 2016-08-19 3:20 [dpdk-dev] [PATCH] net/i40e: fix parsing QinQ packets type issue Beilei Xing @ 2016-08-21 1:21 ` Wu, Jingjing 2016-08-23 9:44 ` [dpdk-dev] [PATCH v2] " Beilei Xing 1 sibling, 0 replies; 7+ messages in thread From: Wu, Jingjing @ 2016-08-21 1:21 UTC (permalink / raw) To: Xing, Beilei; +Cc: dev > -----Original Message----- > From: Xing, Beilei > Sent: Friday, August 19, 2016 11:20 AM > To: Wu, Jingjing <jingjing.wu@intel.com> > Cc: dev@dpdk.org; Xing, Beilei <beilei.xing@intel.com> > Subject: [PATCH] net/i40e: fix parsing QinQ packets type issue > > Previously, PTYPE filed in the RX descriptors is not set properly > for QinQ packets, wrong PTYPE is generated because outer Tag did > not have ORT/PIT configured. > Fix this issue by configuring ORT/PIT. > > Fixes: 4861cde46116 ("i40e: new poll mode driver") > > Signed-off-by: Beilei Xing <beilei.xing@intel.com> > --- > drivers/net/i40e/i40e_ethdev.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c > index 55c4887..ba0eca0 100644 > --- a/drivers/net/i40e/i40e_ethdev.c > +++ b/drivers/net/i40e/i40e_ethdev.c > @@ -747,8 +747,10 @@ static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw) > I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031); > I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031); > I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D); > + I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029); Setting of GLQF_ORT(40) and GLQF_PIT(16) is for outer vlan, but not for Flexible payload. So it may not be suitable to put the code in i40e_flex_payload_reg_init. How about change the function's name and add comments in code? > /* GLQF_PIT Registers */ > + I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420); > I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480); > I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440); > } > -- > 2.5.0 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [dpdk-dev] [PATCH v2] net/i40e: fix parsing QinQ packets type issue 2016-08-19 3:20 [dpdk-dev] [PATCH] net/i40e: fix parsing QinQ packets type issue Beilei Xing 2016-08-21 1:21 ` Wu, Jingjing @ 2016-08-23 9:44 ` Beilei Xing 2016-09-05 5:36 ` Wu, Jingjing 2016-09-12 9:41 ` [dpdk-dev] [PATCH v3] " Beilei Xing 1 sibling, 2 replies; 7+ messages in thread From: Beilei Xing @ 2016-08-23 9:44 UTC (permalink / raw) To: jingjing.wu; +Cc: dev, Beilei Xing Previously, PTYPE filed in the RX descriptors is not set properly for QinQ packets, wrong PTYPE is generated because outer Tag did not have ORT/PIT configured. Fix this issue by configuring ORT/PIT. Fixes: 4861cde46116 ("i40e: new poll mode driver") Signed-off-by: Beilei Xing <beilei.xing@intel.com> --- v2 changes: Modify function name and add comments. drivers/net/i40e/i40e_ethdev.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 55c4887..59ff6dc 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -724,10 +724,6 @@ static struct rte_driver rte_i40e_driver = { PMD_REGISTER_DRIVER(rte_i40e_driver, i40e); DRIVER_REGISTER_PCI_TABLE(i40e, pci_id_i40e_map); -/* - * Initialize registers for flexible payload, which should be set by NVM. - * This should be removed from code once it is fixed in NVM. - */ #ifndef I40E_GLQF_ORT #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4)) #endif @@ -735,8 +731,12 @@ DRIVER_REGISTER_PCI_TABLE(i40e, pci_id_i40e_map); #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4)) #endif -static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw) +static inline void i40e_GLQF_reg_init(struct i40e_hw *hw) { + /* + * Initialize registers for flexible payload, which should be set by NVM. + * This should be removed from code once it is fixed in NVM. + */ I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030); I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030); I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B); @@ -747,10 +747,12 @@ static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw) I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031); I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031); I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D); - - /* GLQF_PIT Registers */ I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480); I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440); + + /* Initialize registers for parsing packet type of QinQ */ + I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029); + I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420); } #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808 @@ -1005,11 +1007,12 @@ eth_i40e_dev_init(struct rte_eth_dev *dev) } /* - * To work around the NVM issue,initialize registers - * for flexible payload by software. - * It should be removed once issues are fixed in NVM. + * To work around the NVM issue, initialize registers + * for flexible payload and packet type of QinQ by + * software. It should be removed once issues are fixed + * in NVM. */ - i40e_flex_payload_reg_init(hw); + i40e_GLQF_reg_init(hw); /* Initialize the input set for filters (hash and fd) to default value */ i40e_filter_input_set_init(pf); -- 2.5.0 ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [dpdk-dev] [PATCH v2] net/i40e: fix parsing QinQ packets type issue 2016-08-23 9:44 ` [dpdk-dev] [PATCH v2] " Beilei Xing @ 2016-09-05 5:36 ` Wu, Jingjing 2016-09-12 9:41 ` [dpdk-dev] [PATCH v3] " Beilei Xing 1 sibling, 0 replies; 7+ messages in thread From: Wu, Jingjing @ 2016-09-05 5:36 UTC (permalink / raw) To: Xing, Beilei; +Cc: dev > -----Original Message----- > From: Xing, Beilei > Sent: Tuesday, August 23, 2016 5:45 PM > To: Wu, Jingjing > Cc: dev@dpdk.org; Xing, Beilei > Subject: [PATCH v2] net/i40e: fix parsing QinQ packets type issue > > Previously, PTYPE filed in the RX descriptors is not set properly for QinQ > packets, wrong PTYPE is generated because outer Tag did not have ORT/PIT > configured. > Fix this issue by configuring ORT/PIT. > > Fixes: 4861cde46116 ("i40e: new poll mode driver") > > Signed-off-by: Beilei Xing <beilei.xing@intel.com> Acked-by: Jingjing Wu <jingjing.wu@intel.com> ^ permalink raw reply [flat|nested] 7+ messages in thread
* [dpdk-dev] [PATCH v3] net/i40e: fix parsing QinQ packets type issue 2016-08-23 9:44 ` [dpdk-dev] [PATCH v2] " Beilei Xing 2016-09-05 5:36 ` Wu, Jingjing @ 2016-09-12 9:41 ` Beilei Xing 2016-09-22 7:40 ` Wu, Jingjing 1 sibling, 1 reply; 7+ messages in thread From: Beilei Xing @ 2016-09-12 9:41 UTC (permalink / raw) To: jingjing.wu; +Cc: dev, Beilei Xing Previously, PTYPE filed in the RX descriptors is not set properly for QinQ packets, wrong PTYPE is generated because outer Tag did not have ORT/PIT configured. Fix this issue by configuring ORT/PIT. Otherwise, this patch changes bitmask of outer VLAN tag in L2 header to support RSS and flow director for QinQ. Fixes: 4861cde46116 ("i40e: new poll mode driver") Fixes: 4072d503aaa5 ("i40e: fix VLAN bitmasks for input set") Signed-off-by: Beilei Xing <beilei.xing@intel.com> --- drivers/net/i40e/i40e_ethdev.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 55c4887..be4b530 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -202,7 +202,7 @@ /* Source MAC address */ #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL /* Outer (S-Tag) VLAN tag in the outer L2 header */ -#define I40E_REG_INSET_L2_OUTER_VLAN 0x0200000000000000ULL +#define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL /* Inner (C-Tag) or single VLAN tag in the outer L2 header */ #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL /* Single VLAN tag in the inner L2 header */ @@ -724,10 +724,6 @@ static struct rte_driver rte_i40e_driver = { PMD_REGISTER_DRIVER(rte_i40e_driver, i40e); DRIVER_REGISTER_PCI_TABLE(i40e, pci_id_i40e_map); -/* - * Initialize registers for flexible payload, which should be set by NVM. - * This should be removed from code once it is fixed in NVM. - */ #ifndef I40E_GLQF_ORT #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4)) #endif @@ -735,8 +731,12 @@ DRIVER_REGISTER_PCI_TABLE(i40e, pci_id_i40e_map); #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4)) #endif -static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw) +static inline void i40e_GLQF_reg_init(struct i40e_hw *hw) { + /* + * Initialize registers for flexible payload, which should be set by NVM. + * This should be removed from code once it is fixed in NVM. + */ I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030); I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030); I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B); @@ -747,10 +747,12 @@ static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw) I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031); I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031); I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D); - - /* GLQF_PIT Registers */ I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480); I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440); + + /* Initialize registers for parsing packet type of QinQ */ + I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029); + I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420); } #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808 @@ -1005,11 +1007,12 @@ eth_i40e_dev_init(struct rte_eth_dev *dev) } /* - * To work around the NVM issue,initialize registers - * for flexible payload by software. - * It should be removed once issues are fixed in NVM. + * To work around the NVM issue, initialize registers + * for flexible payload and packet type of QinQ by + * software. It should be removed once issues are fixed + * in NVM. */ - i40e_flex_payload_reg_init(hw); + i40e_GLQF_reg_init(hw); /* Initialize the input set for filters (hash and fd) to default value */ i40e_filter_input_set_init(pf); -- 2.5.0 ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [dpdk-dev] [PATCH v3] net/i40e: fix parsing QinQ packets type issue 2016-09-12 9:41 ` [dpdk-dev] [PATCH v3] " Beilei Xing @ 2016-09-22 7:40 ` Wu, Jingjing 2016-09-23 11:00 ` Bruce Richardson 0 siblings, 1 reply; 7+ messages in thread From: Wu, Jingjing @ 2016-09-22 7:40 UTC (permalink / raw) To: Xing, Beilei; +Cc: dev > -----Original Message----- > From: Xing, Beilei > Sent: Monday, September 12, 2016 5:42 PM > To: Wu, Jingjing > Cc: dev@dpdk.org; Xing, Beilei > Subject: [PATCH v3] net/i40e: fix parsing QinQ packets type issue > > Previously, PTYPE filed in the RX descriptors is not set properly for QinQ > packets, wrong PTYPE is generated because outer Tag did not have ORT/PIT > configured. Fix this issue by configuring ORT/PIT. > Otherwise, this patch changes bitmask of outer VLAN tag in L2 header to > support RSS and flow director for QinQ. > > Fixes: 4861cde46116 ("i40e: new poll mode driver") > Fixes: 4072d503aaa5 ("i40e: fix VLAN bitmasks for input set") > > Signed-off-by: Beilei Xing <beilei.xing@intel.com> Acked-by: Jingjing Wu <jingjing.wu@intel.com> Minor comments: Please add the changes of the version compared with old version. ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [dpdk-dev] [PATCH v3] net/i40e: fix parsing QinQ packets type issue 2016-09-22 7:40 ` Wu, Jingjing @ 2016-09-23 11:00 ` Bruce Richardson 0 siblings, 0 replies; 7+ messages in thread From: Bruce Richardson @ 2016-09-23 11:00 UTC (permalink / raw) To: Wu, Jingjing; +Cc: Xing, Beilei, dev On Thu, Sep 22, 2016 at 07:40:20AM +0000, Wu, Jingjing wrote: > > > > -----Original Message----- > > From: Xing, Beilei > > Sent: Monday, September 12, 2016 5:42 PM > > To: Wu, Jingjing > > Cc: dev@dpdk.org; Xing, Beilei > > Subject: [PATCH v3] net/i40e: fix parsing QinQ packets type issue > > > > Previously, PTYPE filed in the RX descriptors is not set properly for QinQ > > packets, wrong PTYPE is generated because outer Tag did not have ORT/PIT > > configured. Fix this issue by configuring ORT/PIT. > > Otherwise, this patch changes bitmask of outer VLAN tag in L2 header to > > support RSS and flow director for QinQ. > > > > Fixes: 4861cde46116 ("i40e: new poll mode driver") > > Fixes: 4072d503aaa5 ("i40e: fix VLAN bitmasks for input set") > > > > Signed-off-by: Beilei Xing <beilei.xing@intel.com> > Acked-by: Jingjing Wu <jingjing.wu@intel.com> > Applied to dpdk-next-net/rel_16_11 /Bruce ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2016-09-23 11:00 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2016-08-19 3:20 [dpdk-dev] [PATCH] net/i40e: fix parsing QinQ packets type issue Beilei Xing 2016-08-21 1:21 ` Wu, Jingjing 2016-08-23 9:44 ` [dpdk-dev] [PATCH v2] " Beilei Xing 2016-09-05 5:36 ` Wu, Jingjing 2016-09-12 9:41 ` [dpdk-dev] [PATCH v3] " Beilei Xing 2016-09-22 7:40 ` Wu, Jingjing 2016-09-23 11:00 ` Bruce Richardson
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