From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 61FEB6AE0 for ; Mon, 10 Oct 2016 15:26:18 +0200 (CEST) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga101.fm.intel.com with ESMTP; 10 Oct 2016 06:26:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,324,1473145200"; d="scan'208";a="18034564" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by fmsmga005.fm.intel.com with ESMTP; 10 Oct 2016 06:26:01 -0700 Received: from fmsmsx120.amr.corp.intel.com (10.18.124.208) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.248.2; Mon, 10 Oct 2016 06:26:01 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx120.amr.corp.intel.com (10.18.124.208) with Microsoft SMTP Server (TLS) id 14.3.248.2; Mon, 10 Oct 2016 06:26:00 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.234]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.101]) with mapi id 14.03.0248.002; Mon, 10 Oct 2016 21:25:58 +0800 From: "Wu, Jingjing" To: "Yigit, Ferruh" , Vladyslav Buslov , "Zhang, Helin" CC: "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH] net/i40e: add additional prefetch instructions for bulk rx Thread-Index: AQHSDotogqz+XeyT3kaw6xyn1JzkmaCh0nKg Date: Mon, 10 Oct 2016 13:25:57 +0000 Message-ID: <9BB6961774997848B5B42BEC655768F80E277DFC@SHSMSX103.ccr.corp.intel.com> References: <20160714172719.17502-1-vladyslav.buslov@harmonicinc.com> <20160714172719.17502-2-vladyslav.buslov@harmonicinc.com> <18156776-3658-a97d-3fbc-19c1a820a04d@intel.com> In-Reply-To: <18156776-3658-a97d-3fbc-19c1a820a04d@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMjQ0ODk5OTAtYzcxMy00NGE2LWI1NjAtODRlZTkyNzRhMjBlIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6IitONzJWOGU0Zk8rUDYzditkN2RWdm5DVFhEOTVNOFwvWUdZajdGMjdJK0hRPSJ9 x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] net/i40e: add additional prefetch instructions for bulk rx X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 10 Oct 2016 13:26:19 -0000 > -----Original Message----- > From: Yigit, Ferruh > Sent: Wednesday, September 14, 2016 9:25 PM > To: Vladyslav Buslov ; Zhang, Helin > ; Wu, Jingjing > Cc: dev@dpdk.org > Subject: Re: [dpdk-dev] [PATCH] net/i40e: add additional prefetch instruc= tions for bulk rx >=20 > On 7/14/2016 6:27 PM, Vladyslav Buslov wrote: > > Added prefetch of first packet payload cacheline in i40e_rx_scan_hw_rin= g > > Added prefetch of second mbuf cacheline in i40e_rx_alloc_bufs > > > > Signed-off-by: Vladyslav Buslov > > --- > > drivers/net/i40e/i40e_rxtx.c | 7 +++++-- > > 1 file changed, 5 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.= c > > index d3cfb98..e493fb4 100644 > > --- a/drivers/net/i40e/i40e_rxtx.c > > +++ b/drivers/net/i40e/i40e_rxtx.c > > @@ -1003,6 +1003,7 @@ i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq) > > /* Translate descriptor info to mbuf parameters */ > > for (j =3D 0; j < nb_dd; j++) { > > mb =3D rxep[j].mbuf; > > + rte_prefetch0(RTE_PTR_ADD(mb->buf_addr, > RTE_PKTMBUF_HEADROOM)); Why did prefetch here? I think if application need to deal with packet, it = is more suitable to put it in application. > > qword1 =3D rte_le_to_cpu_64(\ > > rxdp[j].wb.qword1.status_error_len); > > pkt_len =3D ((qword1 & > I40E_RXD_QW1_LENGTH_PBUF_MASK) >> > > @@ -1086,9 +1087,11 @@ i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq) > > > > rxdp =3D &rxq->rx_ring[alloc_idx]; > > for (i =3D 0; i < rxq->rx_free_thresh; i++) { > > - if (likely(i < (rxq->rx_free_thresh - 1))) > > + if (likely(i < (rxq->rx_free_thresh - 1))) { > > /* Prefetch next mbuf */ > > - rte_prefetch0(rxep[i + 1].mbuf); > > + rte_prefetch0(&rxep[i + 1].mbuf->cacheline0); > > + rte_prefetch0(&rxep[i + 1].mbuf->cacheline1); > > + } Agree with this change. And when I test it by testpmd with iofwd, no perfor= mance increase is observed but minor decrease. Can you share will us when it will benefit the performance in your scenario= ?=20 Thanks Jingjing