From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 4A4593DC for ; Mon, 26 Dec 2016 09:45:45 +0100 (CET) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP; 26 Dec 2016 00:45:44 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,404,1477983600"; d="scan'208";a="43365547" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga004.jf.intel.com with ESMTP; 26 Dec 2016 00:45:44 -0800 Received: from fmsmsx122.amr.corp.intel.com (10.18.125.37) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.248.2; Mon, 26 Dec 2016 00:45:44 -0800 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx122.amr.corp.intel.com (10.18.125.37) with Microsoft SMTP Server (TLS) id 14.3.248.2; Mon, 26 Dec 2016 00:45:44 -0800 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.20]) by SHSMSX104.ccr.corp.intel.com ([10.239.4.70]) with mapi id 14.03.0248.002; Mon, 26 Dec 2016 16:45:42 +0800 From: "Wu, Jingjing" To: "Sexton, Rory" CC: "dev@dpdk.org" , "Marjanovic, Nemanja" , "Mcnamara, John" Thread-Topic: [PATCH v1] net/i40e: set no drop for traffic class Thread-Index: AQHSTjYCOqbbcDGaEEOO58x9QoWgHqD5BVpAgAYh94CAGuFfAA== Date: Mon, 26 Dec 2016 08:45:41 +0000 Message-ID: <9BB6961774997848B5B42BEC655768F810CBEF56@SHSMSX103.ccr.corp.intel.com> References: <1480859687-27047-1-git-send-email-rory.sexton@intel.com> <9BB6961774997848B5B42BEC655768F80E2C29D0@SHSMSX103.ccr.corp.intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v1] net/i40e: set no drop for traffic class X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 26 Dec 2016 08:45:46 -0000 > -----Original Message----- > From: Sexton, Rory > Sent: Friday, December 9, 2016 10:03 PM > To: Wu, Jingjing > Cc: dev@dpdk.org; Marjanovic, Nemanja ; > Mcnamara, John > Subject: RE: [PATCH v1] net/i40e: set no drop for traffic class >=20 > Hi Jingjing, >=20 > Yes PRTDCB_TC2PFC is used to control pfc for each TC however we have > noticed other advantages of using the register. > By setting the register explicitly by doing the "I40E_WRITE_REG(hw, 0x1c0= 980, > 0xff);" it allows for packets to be temporarily stored on the NICs RX SRA= M > until there is space for them on SW descriptor ring versus dropping them > when the SW ring becomes full. This also allows for larger burst handling= . It > also means SW doesn't have to be as quick to empty the DRAM based > descriptor rings, allowing more processing on cores. >=20 > I have tested using the ETH_DCB_PFC_SUPPORT flag in > rte_eth_conf.dcb_capability_en and rte_eth_dcb_rx_conf.nb_tcs. > This results in the NIC's RX SRAM not being used and if there is no space= on > SW descriptor ring for packet it is dropped. Besides ETH_DCB_PFC_SUPPORT, ETH_MQ_RX_DCB_FLAG is also required in dev_conf.rxmode.mq_mode. After doing that, you will find register PRTDCB_TC= 2PFC is also changed. =20 If you don't want to enable DCB, why not just implement that function "i40e= _priority_flow_ctrl_set"? You can change the register in this function without define a new API. > The advantages of using the PRTDCB_TC2PFC explicitly is that there will b= e no > packet loss and descriptor rings do not need to be modified (can be left = at > 128 for rx and 512 for tx as default settings for apps). Enabling via th= is > register allows Burst handling to be within the NIC Rx Buffer and SW ring= s > combined. > At the moment for tests the rx and tx descriptor rings have to be increas= ed > to 2048 to eliminate packet loss. >=20 > Ideally it would be an optional setting as using it may increase the max > latency. >=20 Thanks for the clarification. Thanks Jingjing