From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 8D85510B88 for ; Thu, 30 Mar 2017 08:16:58 +0200 (CEST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP; 29 Mar 2017 23:16:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,245,1486454400"; d="scan'208";a="1128783229" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by fmsmga001.fm.intel.com with ESMTP; 29 Mar 2017 23:16:57 -0700 Received: from fmsmsx121.amr.corp.intel.com (10.18.125.36) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 29 Mar 2017 23:16:56 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx121.amr.corp.intel.com (10.18.125.36) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 29 Mar 2017 23:16:56 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.253]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.42]) with mapi id 14.03.0248.002; Thu, 30 Mar 2017 14:16:54 +0800 From: "Wu, Jingjing" To: "Xing, Beilei" CC: "Zhang, Helin" , "Iremonger, Bernard" , "dev@dpdk.org" Thread-Topic: [PATCH v4 4/4] net/i40e: enable tunnel filter for MPLS Thread-Index: AQHSqQtlyafLbg8Q6kyqKlUdc+aphaGs55rw Date: Thu, 30 Mar 2017 06:16:54 +0000 Message-ID: <9BB6961774997848B5B42BEC655768F810D1B13E@SHSMSX103.ccr.corp.intel.com> References: <1490683208-38096-1-git-send-email-beilei.xing@intel.com> <1490846875-30484-1-git-send-email-beilei.xing@intel.com> <1490846875-30484-5-git-send-email-beilei.xing@intel.com> In-Reply-To: <1490846875-30484-5-git-send-email-beilei.xing@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v4 4/4] net/i40e: enable tunnel filter for MPLS X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 30 Mar 2017 06:16:59 -0000 > int > i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf, > struct i40e_tunnel_filter_conf *tunnel_filter, @@ -6954,6 > +7063,8 @@ i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf, > struct i40e_tunnel_rule *tunnel_rule =3D &pf->tunnel; > struct i40e_tunnel_filter *tunnel, *node; > struct i40e_tunnel_filter check_filter; /* Check if filter exists */ > + uint32_t teid_le; > + bool big_buffer =3D 0; >=20 > cld_filter =3D rte_zmalloc("tunnel_filter", > sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext), > @@ -7001,6 +7112,32 @@ i40e_dev_consistent_tunnel_filter_set(struct > i40e_pf *pf, > case I40E_TUNNEL_TYPE_IP_IN_GRE: > tun_type =3D I40E_AQC_ADD_CLOUD_TNL_TYPE_IP; > break; > + case I40E_TUNNEL_TYPE_MPLSoUDP: > + i40e_replace_mpls_l1_filter(pf); > + i40e_replace_mpls_cloud_filter(pf); Do we need replace every time when add each rule? Thanks Jingjing