From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: <jingjing.wu@intel.com> Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 6B000594B for <dev@dpdk.org>; Fri, 8 May 2015 05:21:51 +0200 (CEST) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP; 07 May 2015 20:21:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.13,387,1427785200"; d="scan'208";a="568166861" Received: from pgsmsx102.gar.corp.intel.com ([10.221.44.80]) by orsmga003.jf.intel.com with ESMTP; 07 May 2015 20:21:49 -0700 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by PGSMSX102.gar.corp.intel.com (10.221.44.80) with Microsoft SMTP Server (TLS) id 14.3.224.2; Fri, 8 May 2015 11:21:48 +0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.162]) by shsmsx102.ccr.corp.intel.com ([10.239.4.154]) with mapi id 14.03.0224.002; Fri, 8 May 2015 11:21:47 +0800 From: "Wu, Jingjing" <jingjing.wu@intel.com> To: "Zhang, Helin" <helin.zhang@intel.com>, "dev@dpdk.org" <dev@dpdk.org> Thread-Topic: [PATCH v2 03/33] i40e: adjustment of register definitions and relevant Thread-Index: AQHQg1bzik6QeNn0IUCmltJ6XSfnvp1xdYVg Date: Fri, 8 May 2015 03:21:47 +0000 Message-ID: <9BB6961774997848B5B42BEC655768F8C18318@SHSMSX104.ccr.corp.intel.com> References: <1429518150-28098-1-git-send-email-helin.zhang@intel.com> <1430406219-23901-1-git-send-email-helin.zhang@intel.com> <1430406219-23901-4-git-send-email-helin.zhang@intel.com> In-Reply-To: <1430406219-23901-4-git-send-email-helin.zhang@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Cc: "Kenguva, Monica" <monica.kenguva@intel.com>, "Murray, Steven J" <steven.j.murray@intel.com>, "Nelson, Shannon" <shannon.nelson@intel.com> Subject: Re: [dpdk-dev] [PATCH v2 03/33] i40e: adjustment of register definitions and relevant X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK <dev.dpdk.org> List-Unsubscribe: <http://dpdk.org/ml/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://dpdk.org/ml/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <http://dpdk.org/ml/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> X-List-Received-Date: Fri, 08 May 2015 03:21:52 -0000 Acked-by: Jingjing Wu <jingjing.wu@intel.com> > -----Original Message----- > From: Zhang, Helin > Sent: Thursday, April 30, 2015 11:03 PM > To: dev@dpdk.org > Cc: Cao, Min; Xu, Qian Q; Wu, Jingjing; Liu, Jijiang; Kenguva, Monica; Pa= tel, > Rashmin N; Murray, Steven J; Nelson, Shannon; Zhang, Helin > Subject: [PATCH v2 03/33] i40e: adjustment of register definitions and > relevant >=20 > Some macros of register definitions or relevant are added, modified or > deleted. In detail, they are as follows. > - I40E_PRTDCB_RUPTQ > - I40E_GLGEN_GPIO_CTL > - I40E_GLGEN_MDIO_CTRL > - I40E_GLGEN_RSTENA_EMP > - I40E_GLPCI_LATCT > - I40E_GLTPH_CTRL > - I40E_GLPRT_BPRCH > - I40E_GLPRT_TDPC > - I40E_GLSCD_QUANTA > Also reading the register of I40E_GLPRT_TDPC is deleted as its definition= is > deleted. >=20 > Signed-off-by: Helin Zhang <helin.zhang@intel.com> > --- > lib/librte_pmd_i40e/i40e/i40e_register.h | 52 ++++++++++++++++----------= -- > ---- > lib/librte_pmd_i40e/i40e_ethdev.c | 3 -- > 2 files changed, 26 insertions(+), 29 deletions(-) >=20 > v2 changes: > Removed anything about Fortpark or FPGA as they shouldn't be there. >=20 > diff --git a/lib/librte_pmd_i40e/i40e/i40e_register.h > b/lib/librte_pmd_i40e/i40e/i40e_register.h > index 888c3c3..c8a8d77 100644 > --- a/lib/librte_pmd_i40e/i40e/i40e_register.h > +++ b/lib/librte_pmd_i40e/i40e/i40e_register.h > @@ -318,6 +318,10 @@ POSSIBILITY OF SUCH DAMAGE. > #define I40E_PRTDCB_RUP2TC_UP6TC_MASK I40E_MASK(0x7, > I40E_PRTDCB_RUP2TC_UP6TC_SHIFT) #define > I40E_PRTDCB_RUP2TC_UP7TC_SHIFT 21 #define > I40E_PRTDCB_RUP2TC_UP7TC_MASK I40E_MASK(0x7, > I40E_PRTDCB_RUP2TC_UP7TC_SHIFT) > +#define I40E_PRTDCB_RUPTQ(_i) (0x00122400 + ((_i) * 32)) /* > _i=3D0...7 */ /* Reset: CORER */ > +#define I40E_PRTDCB_RUPTQ_MAX_INDEX 7 > +#define I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT 0 #define > +I40E_PRTDCB_RUPTQ_RXQNUM_MASK I40E_MASK(0x3FFF, > +I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT) > #define I40E_PRTDCB_TC2PFC 0x001C0980 /* Reset: CORER */ > #define I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT 0 #define > I40E_PRTDCB_TC2PFC_TC2PFC_MASK I40E_MASK(0xFF, > I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT) @@ -429,6 +433,8 @@ POSSIBILITY > OF SUCH DAMAGE. > #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_MASK I40E_MASK(0x1, > I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT) > #define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT 20 #define > I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_MASK I40E_MASK(0x3F, > I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT) > +#define I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_SHIFT 26 > +#define I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_MASK I40E_MASK(0xF, > I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_SHIFT) > #define I40E_GLGEN_GPIO_SET 0x00088184 /* Reset: POR */ > #define I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT 0 #define > I40E_GLGEN_GPIO_SET_GPIO_INDX_MASK I40E_MASK(0x1F, > I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT) > @@ -492,7 +498,9 @@ POSSIBILITY OF SUCH DAMAGE. > #define I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT 17 > #define I40E_GLGEN_MDIO_CTRL_CONTMDC_MASK I40E_MASK(0x1, > I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT) > #define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT 18 -#define > I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_MASK I40E_MASK(0x3FFF, > I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT) > +#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_MASK > I40E_MASK(0x7FF, > +I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT) > +#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_SHIFT 29 #define > +I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_MASK I40E_MASK(0x7, > +I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_SHIFT) > #define I40E_GLGEN_MDIO_I2C_SEL(_i) (0x000881C0 + ((_i) *= 4)) > /* _i=3D0...3 */ /* Reset: POR */ > #define I40E_GLGEN_MDIO_I2C_SEL_MAX_INDEX 3 > #define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT 0 @@ -556,9 > +564,6 @@ POSSIBILITY OF SUCH DAMAGE. > #define I40E_GLGEN_RSTCTL_GRSTDEL_MASK I40E_MASK(0x3F, > I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT) > #define I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT 8 #define > I40E_GLGEN_RSTCTL_ECC_RST_ENA_MASK I40E_MASK(0x1, > I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT) > -#define I40E_GLGEN_RSTENA_EMP 0x000B818C /* Reset: POR > */ > -#define I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_SHIFT 0 -#define > I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK I40E_MASK(0x1, > I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_SHIFT) > #define I40E_GLGEN_RTRIG 0x000B8190 /* Reset: CORER */ > #define I40E_GLGEN_RTRIG_CORER_SHIFT 0 > #define I40E_GLGEN_RTRIG_CORER_MASK I40E_MASK(0x1, > I40E_GLGEN_RTRIG_CORER_SHIFT) > @@ -1074,7 +1079,7 @@ POSSIBILITY OF SUCH DAMAGE. > #define I40E_PFINT_RATEN_INTERVAL_MASK I40E_MASK(0x3F, > I40E_PFINT_RATEN_INTERVAL_SHIFT) > #define I40E_PFINT_RATEN_INTRL_ENA_SHIFT 6 #define > I40E_PFINT_RATEN_INTRL_ENA_MASK I40E_MASK(0x1, > I40E_PFINT_RATEN_INTRL_ENA_SHIFT) > -#define I40E_PFINT_STAT_CTL0 0x00038400 /* Reset: P= FR */ > +#define I40E_PFINT_STAT_CTL0 0x00038400 /* Reset: C= ORER > */ > #define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2 #define > I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK I40E_MASK(0x3, > I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT) > #define I40E_QINT_RQCTL(_Q) (0x0003A000 + ((_Q) * 4)) /* > _i=3D0...1535 */ /* Reset: CORER */ > @@ -1179,7 +1184,7 @@ POSSIBILITY OF SUCH DAMAGE. > #define I40E_VFINT_ITRN_MAX_INDEX 2 > #define I40E_VFINT_ITRN_INTERVAL_SHIFT 0 #define > I40E_VFINT_ITRN_INTERVAL_MASK I40E_MASK(0xFFF, > I40E_VFINT_ITRN_INTERVAL_SHIFT) > -#define I40E_VFINT_STAT_CTL0(_VF) (0x0002A000 + ((_VF) *= 4)) > /* _i=3D0...127 */ /* Reset: VFR */ > +#define I40E_VFINT_STAT_CTL0(_VF) (0x0002A000 + ((_VF) *= 4)) > /* _i=3D0...127 */ /* Reset: CORER */ > #define I40E_VFINT_STAT_CTL0_MAX_INDEX 127 > #define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2 #define > I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_MASK I40E_MASK(0x3, > I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT) > @@ -1811,9 +1816,6 @@ POSSIBILITY OF SUCH DAMAGE. > #define I40E_GLPCI_GSCN_0_3_MAX_INDEX 3 > #define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT 0 #define > I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_MASK I40E_MASK(0xFFFFFFFF, > I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT) > -#define I40E_GLPCI_LATCT 0x0009C4B4 /* Reset: PCI= R */ > -#define I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_SHIFT 0 -#define > I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_MASK I40E_MASK(0xFFFFFFFF, > I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_SHIFT) > #define I40E_GLPCI_LBARCTRL 0x000BE484 /* Reset: POR = */ > #define I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT 0 > #define I40E_GLPCI_LBARCTRL_PREFBAR_MASK I40E_MASK(0x1, > I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT) > @@ -1910,6 +1912,11 @@ POSSIBILITY OF SUCH DAMAGE. > #define I40E_GLPCI_VFSUP_VF_PREFETCH_MASK I40E_MASK(0x1, > I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT) > #define I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT 1 #define > I40E_GLPCI_VFSUP_VR_BAR_TYPE_MASK I40E_MASK(0x1, > I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT) > +#define I40E_GLTPH_CTRL 0x000BE480 /* Reset: PCI= R */ > +#define I40E_GLTPH_CTRL_DESC_PH_SHIFT 9 > +#define I40E_GLTPH_CTRL_DESC_PH_MASK I40E_MASK(0x3, > I40E_GLTPH_CTRL_DESC_PH_SHIFT) > +#define I40E_GLTPH_CTRL_DATA_PH_SHIFT 11 > +#define I40E_GLTPH_CTRL_DATA_PH_MASK I40E_MASK(0x3, > I40E_GLTPH_CTRL_DATA_PH_SHIFT) > #define I40E_PF_FUNC_RID 0x0009C000 /* Reset: PCIR= */ > #define I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT 0 #define > I40E_PF_FUNC_RID_FUNCTION_NUMBER_MASK I40E_MASK(0x7, > I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT) > @@ -2382,20 +2389,20 @@ POSSIBILITY OF SUCH DAMAGE. > #define I40E_GL_RXERR2_L_FCOEDIXAC_MASK I40E_MASK(0xFFFFFFFF, > I40E_GL_RXERR2_L_FCOEDIXAC_SHIFT) > #define I40E_GLPRT_BPRCH(_i) (0x003005E4 + ((_i) * 8)) /* _i=3D0= ...3 */ > /* Reset: CORER */ > #define I40E_GLPRT_BPRCH_MAX_INDEX 3 > -#define I40E_GLPRT_BPRCH_UPRCH_SHIFT 0 > -#define I40E_GLPRT_BPRCH_UPRCH_MASK I40E_MASK(0xFFFF, > I40E_GLPRT_BPRCH_UPRCH_SHIFT) > +#define I40E_GLPRT_BPRCH_BPRCH_SHIFT 0 > +#define I40E_GLPRT_BPRCH_BPRCH_MASK I40E_MASK(0xFFFF, > +I40E_GLPRT_BPRCH_BPRCH_SHIFT) > #define I40E_GLPRT_BPRCL(_i) (0x003005E0 + ((_i) * 8)) /* _i=3D0= ...3 */ > /* Reset: CORER */ > #define I40E_GLPRT_BPRCL_MAX_INDEX 3 > -#define I40E_GLPRT_BPRCL_UPRCH_SHIFT 0 > -#define I40E_GLPRT_BPRCL_UPRCH_MASK I40E_MASK(0xFFFFFFFF, > I40E_GLPRT_BPRCL_UPRCH_SHIFT) > +#define I40E_GLPRT_BPRCL_BPRCL_SHIFT 0 > +#define I40E_GLPRT_BPRCL_BPRCL_MASK I40E_MASK(0xFFFFFFFF, > +I40E_GLPRT_BPRCL_BPRCL_SHIFT) > #define I40E_GLPRT_BPTCH(_i) (0x00300A04 + ((_i) * 8)) /* _i=3D0= ...3 */ > /* Reset: CORER */ > #define I40E_GLPRT_BPTCH_MAX_INDEX 3 > -#define I40E_GLPRT_BPTCH_UPRCH_SHIFT 0 > -#define I40E_GLPRT_BPTCH_UPRCH_MASK I40E_MASK(0xFFFF, > I40E_GLPRT_BPTCH_UPRCH_SHIFT) > +#define I40E_GLPRT_BPTCH_BPTCH_SHIFT 0 > +#define I40E_GLPRT_BPTCH_BPTCH_MASK I40E_MASK(0xFFFF, > +I40E_GLPRT_BPTCH_BPTCH_SHIFT) > #define I40E_GLPRT_BPTCL(_i) (0x00300A00 + ((_i) * 8)) /* _i=3D0= ...3 */ > /* Reset: CORER */ > #define I40E_GLPRT_BPTCL_MAX_INDEX 3 > -#define I40E_GLPRT_BPTCL_UPRCH_SHIFT 0 > -#define I40E_GLPRT_BPTCL_UPRCH_MASK I40E_MASK(0xFFFFFFFF, > I40E_GLPRT_BPTCL_UPRCH_SHIFT) > +#define I40E_GLPRT_BPTCL_BPTCL_SHIFT 0 > +#define I40E_GLPRT_BPTCL_BPTCL_MASK I40E_MASK(0xFFFFFFFF, > +I40E_GLPRT_BPTCL_BPTCL_SHIFT) > #define I40E_GLPRT_CRCERRS(_i) (0x00300080 + ((_i) * 8)) /* > _i=3D0...3 */ /* Reset: CORER */ > #define I40E_GLPRT_CRCERRS_MAX_INDEX 3 > #define I40E_GLPRT_CRCERRS_CRCERRS_SHIFT 0 @@ -2628,10 +2635,6 > @@ POSSIBILITY OF SUCH DAMAGE. > #define I40E_GLPRT_TDOLD_MAX_INDEX 3 > #define I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT 0 #define > I40E_GLPRT_TDOLD_GLPRT_TDOLD_MASK I40E_MASK(0xFFFFFFFF, > I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT) > -#define I40E_GLPRT_TDPC(_i) (0x00375400 + ((_i) * 8)) /* _i=3D0..= .3 */ > /* Reset: CORER */ > -#define I40E_GLPRT_TDPC_MAX_INDEX 3 > -#define I40E_GLPRT_TDPC_TDPC_SHIFT 0 > -#define I40E_GLPRT_TDPC_TDPC_MASK I40E_MASK(0xFFFFFFFF, > I40E_GLPRT_TDPC_TDPC_SHIFT) > #define I40E_GLPRT_UPRCH(_i) (0x003005A4 + ((_i) * 8)) /* _i=3D0= ...3 */ > /* Reset: CORER */ > #define I40E_GLPRT_UPRCH_MAX_INDEX 3 > #define I40E_GLPRT_UPRCH_UPRCH_SHIFT 0 > @@ -2998,9 +3001,6 @@ POSSIBILITY OF SUCH DAMAGE. > #define I40E_PRTTSYN_TXTIME_L 0x001E41C0 /* Reset: GLOBR = */ > #define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT 0 #define > I40E_PRTTSYN_TXTIME_L_TXTIEM_L_MASK I40E_MASK(0xFFFFFFFF, > I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT) > -#define I40E_GLSCD_QUANTA 0x000B2080 /* Reset: CORER */ > -#define I40E_GLSCD_QUANTA_TSCDQUANTA_SHIFT 0 -#define > I40E_GLSCD_QUANTA_TSCDQUANTA_MASK I40E_MASK(0x7, > I40E_GLSCD_QUANTA_TSCDQUANTA_SHIFT) > #define I40E_GL_MDET_RX 0x0012A510 /* Reset: CORER */ > #define I40E_GL_MDET_RX_FUNCTION_SHIFT 0 #define > I40E_GL_MDET_RX_FUNCTION_MASK I40E_MASK(0xFF, > I40E_GL_MDET_RX_FUNCTION_SHIFT) @@ -3266,7 +3266,7 @@ > POSSIBILITY OF SUCH DAMAGE. > #define I40E_VFINT_ITRN1_MAX_INDEX 2 > #define I40E_VFINT_ITRN1_INTERVAL_SHIFT 0 #define > I40E_VFINT_ITRN1_INTERVAL_MASK I40E_MASK(0xFFF, > I40E_VFINT_ITRN1_INTERVAL_SHIFT) > -#define I40E_VFINT_STAT_CTL01 0x00005400 /* Reset: = VFR */ > +#define I40E_VFINT_STAT_CTL01 0x00005400 /* Reset: > CORER */ > #define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2 #define > I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_MASK I40E_MASK(0x3, > I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT) > #define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=3D0...= 15 */ > /* Reset: CORER */ > @@ -3374,4 +3374,4 @@ POSSIBILITY OF SUCH DAMAGE. > #define I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, > I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT) > #define I40E_VFQF_HREGION_REGION_7_SHIFT 29 > #define I40E_VFQF_HREGION_REGION_7_MASK I40E_MASK(0x7, > I40E_VFQF_HREGION_REGION_7_SHIFT) > -#endif > +#endif /* _I40E_REGISTER_H_ */ > diff --git a/lib/librte_pmd_i40e/i40e_ethdev.c > b/lib/librte_pmd_i40e/i40e_ethdev.c > index 49d1067..3d45429 100644 > --- a/lib/librte_pmd_i40e/i40e_ethdev.c > +++ b/lib/librte_pmd_i40e/i40e_ethdev.c > @@ -1269,9 +1269,6 @@ i40e_dev_stats_get(struct rte_eth_dev *dev, > struct rte_eth_stats *stats) > I40E_GLPRT_BPTCL(hw->port), > pf->offset_loaded, &os->eth.tx_broadcast, > &ns->eth.tx_broadcast); > - i40e_stat_update_32(hw, I40E_GLPRT_TDPC(hw->port), > - pf->offset_loaded, &os->eth.tx_discards, > - &ns->eth.tx_discards); > /* GLPRT_TEPC not supported */ >=20 > /* additional port specific stats */ > -- > 1.8.1.4