From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 68B922A5E for ; Thu, 9 Jul 2015 05:32:40 +0200 (CEST) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP; 08 Jul 2015 20:32:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,436,1432623600"; d="scan'208";a="602754610" Received: from pgsmsx103.gar.corp.intel.com ([10.221.44.82]) by orsmga003.jf.intel.com with ESMTP; 08 Jul 2015 20:32:38 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by PGSMSX103.gar.corp.intel.com (10.221.44.82) with Microsoft SMTP Server (TLS) id 14.3.224.2; Thu, 9 Jul 2015 11:31:29 +0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.129]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.157]) with mapi id 14.03.0224.002; Thu, 9 Jul 2015 11:31:28 +0800 From: "Wu, Jingjing" To: "Tao, Zhe" , "dev@dpdk.org" Thread-Topic: [PATCH v3] i40e:Fix the Descriptor Done check mechanism for i40e Thread-Index: AQHQufMiozAwBAnksEKYolTcc0Rr1p3SevFQ Date: Thu, 9 Jul 2015 03:31:27 +0000 Message-ID: <9BB6961774997848B5B42BEC655768F8C6473D@SHSMSX104.ccr.corp.intel.com> References: <1436347759-31915-1-git-send-email-zhe.tao@intel.com> <1436410688-663-1-git-send-email-zhe.tao@intel.com> In-Reply-To: <1436410688-663-1-git-send-email-zhe.tao@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v3] i40e:Fix the Descriptor Done check mechanism for i40e X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 09 Jul 2015 03:32:41 -0000 Acked-by: Jingjing Wu > -----Original Message----- > From: Tao, Zhe > Sent: Thursday, July 09, 2015 10:58 AM > To: dev@dpdk.org > Cc: Tao, Zhe; Wu, Jingjing > Subject: [PATCH v3] i40e:Fix the Descriptor Done check mechanism for i40e >=20 > If a descriptor the device drive is handling is the context descriptor, i= ts type > value will be 0x1. > When using the not operator ! to do the conditional check, if the express= ion > value is zero, the device driver will consider the transaction for this d= escriptor > has been completed, even its DD field is still 0x1 which means NIC has no= t > finished the operation on this descriptor. > Use the 0xF to check the DD status to avoid the above issue happens. >=20 > Signed-off-by: Zhe Tao > --- >=20 > Patch v3 changes: > -Fix typo for the patch >=20 > Patch v2 changes: > -Fix the DD check mechanism for other functions (besides the > i40e_xmit_cleanup) which use the DD bits to do conditional check >=20 > changes: > -Fix the DD check mechanism for i40e_xmit_cleanup >=20 > drivers/net/i40e/i40e_fdir.c | 3 ++- > drivers/net/i40e/i40e_rxtx.c | 10 ++++++---- > 2 files changed, 8 insertions(+), 5 deletions(-) >=20 > diff --git a/drivers/net/i40e/i40e_fdir.c b/drivers/net/i40e/i40e_fdir.c = index > 4bf98d0..f3cb757 100644 > --- a/drivers/net/i40e/i40e_fdir.c > +++ b/drivers/net/i40e/i40e_fdir.c > @@ -1110,7 +1110,8 @@ i40e_fdir_filter_programming(struct i40e_pf *pf, >=20 > for (i =3D 0; i < I40E_FDIR_WAIT_COUNT; i++) { > rte_delay_us(I40E_FDIR_WAIT_INTERVAL_US); > - if (txdp->cmd_type_offset_bsz & > + if ((txdp->cmd_type_offset_bsz & > + > rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) =3D=3D >=20 > rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) > break; > } > diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c = index > 2de0ac4..7c0c684 100644 > --- a/drivers/net/i40e/i40e_rxtx.c > +++ b/drivers/net/i40e/i40e_rxtx.c > @@ -574,8 +574,9 @@ i40e_xmit_cleanup(struct i40e_tx_queue *txq) > desc_to_clean_to =3D (uint16_t)(desc_to_clean_to - > nb_tx_desc); >=20 > desc_to_clean_to =3D sw_ring[desc_to_clean_to].last_id; > - if (!(txd[desc_to_clean_to].cmd_type_offset_bsz & > - rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))) { > + if ((txd[desc_to_clean_to].cmd_type_offset_bsz & > + > rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=3D > + > rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) { > PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done > " > "(port=3D%d queue=3D%d)", desc_to_clean_to, > txq->port_id, txq->queue_id); > @@ -1431,8 +1432,9 @@ i40e_tx_free_bufs(struct i40e_tx_queue *txq) > struct i40e_tx_entry *txep; > uint16_t i; >=20 > - if (!(txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz & > - > rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))) > + if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz & > + > rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=3D > + > rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) > return 0; >=20 > txep =3D &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]); > -- > 1.8.4.2