From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id F41B3DE4 for ; Wed, 15 Jul 2015 03:02:40 +0200 (CEST) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP; 14 Jul 2015 18:02:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,476,1432623600"; d="scan'208";a="606338326" Received: from kmsmsx153.gar.corp.intel.com ([172.21.73.88]) by orsmga003.jf.intel.com with ESMTP; 14 Jul 2015 18:02:36 -0700 Received: from shsmsx103.ccr.corp.intel.com (10.239.110.14) by KMSMSX153.gar.corp.intel.com (172.21.73.88) with Microsoft SMTP Server (TLS) id 14.3.224.2; Wed, 15 Jul 2015 09:01:34 +0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.129]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.46]) with mapi id 14.03.0224.002; Wed, 15 Jul 2015 09:01:32 +0800 From: "Wu, Jingjing" To: "Tao, Zhe" , "dev@dpdk.org" Thread-Topic: [PATCH] i40e: Fix the endian issue for the i40e read&write registers functions Thread-Index: AQHQviEJ7+cWTS6sw0mVzpcqUrhHLJ3btsqQ Date: Wed, 15 Jul 2015 01:01:31 +0000 Message-ID: <9BB6961774997848B5B42BEC655768F8C681A1@SHSMSX104.ccr.corp.intel.com> References: <1436870216-12926-1-git-send-email-zhe.tao@intel.com> In-Reply-To: <1436870216-12926-1-git-send-email-zhe.tao@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] i40e: Fix the endian issue for the i40e read&write registers functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 15 Jul 2015 01:02:41 -0000 > -----Original Message----- > From: Tao, Zhe > Sent: Tuesday, July 14, 2015 6:37 PM > To: dev@dpdk.org > Cc: Tao, Zhe; Wu, Jingjing > Subject: [PATCH] i40e: Fix the endian issue for the i40e read&write regis= ters > functions >=20 > Linux kernel uses the writel and readl related functions to perform the P= CI > memory access via ioremap region, those functions will handle the big lit= tle > endian properly by doing the conversion between little and big endian if > necessary, so Add this conversion in the read&write registers functions f= or > i40e. >=20 > Signed-off-by: Zhe Tao > --- > drivers/net/i40e/base/i40e_osdep.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/net/i40e/base/i40e_osdep.h > b/drivers/net/i40e/base/i40e_osdep.h > index 3ce8057..d35c494 100644 > --- a/drivers/net/i40e/base/i40e_osdep.h > +++ b/drivers/net/i40e/base/i40e_osdep.h > @@ -122,10 +122,10 @@ do { = \ > ((volatile uint32_t *)((char *)(a)->hw_addr + (reg))) static inline > uint32_t i40e_read_addr(volatile void *addr) { > - return I40E_PCI_REG(addr); > + return rte_cpu_to_le_32(I40E_PCI_REG(addr)); I think we need use rte_le_to_cpu_32 but not rte_cpu_to_le_32 for reading. > } > #define I40E_PCI_REG_WRITE(reg, value) \ > - do {I40E_PCI_REG((reg)) =3D (value);} while(0) > + do { I40E_PCI_REG((reg)) =3D rte_cpu_to_le_32(value); } while (0) >=20 > #define I40E_WRITE_FLUSH(a) I40E_READ_REG(a, I40E_GLGEN_STAT) > #define I40EVF_WRITE_FLUSH(a) I40E_READ_REG(a, I40E_VFGEN_RSTAT) > -- > 1.9.3