From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id C97545958 for ; Tue, 8 Sep 2015 02:59:44 +0200 (CEST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP; 07 Sep 2015 17:59:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,487,1437462000"; d="scan'208";a="557206302" Received: from kmsmsx153.gar.corp.intel.com ([172.21.73.88]) by FMSMGA003.fm.intel.com with ESMTP; 07 Sep 2015 17:59:43 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by KMSMSX153.gar.corp.intel.com (172.21.73.88) with Microsoft SMTP Server (TLS) id 14.3.224.2; Tue, 8 Sep 2015 08:55:25 +0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.210]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.101]) with mapi id 14.03.0224.002; Tue, 8 Sep 2015 08:55:24 +0800 From: "Wu, Jingjing" To: "Lu, Wenzhuo" , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH] ixgbe: fix a x550 DCB issue Thread-Index: AQHQ385+m5mGox680Emi/ShSqcnXhJ4x4ftA Date: Tue, 8 Sep 2015 00:55:23 +0000 Message-ID: <9BB6961774997848B5B42BEC655768F8CCADE4@SHSMSX104.ccr.corp.intel.com> References: <1440573069-9385-1-git-send-email-wenzhuo.lu@intel.com> In-Reply-To: <1440573069-9385-1-git-send-email-wenzhuo.lu@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] ixgbe: fix a x550 DCB issue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 08 Sep 2015 00:59:45 -0000 > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Wenzhuo Lu > Sent: Wednesday, August 26, 2015 3:11 PM > To: dev@dpdk.org > Subject: [dpdk-dev] [PATCH] ixgbe: fix a x550 DCB issue >=20 > There's a DCB issue on x550. For 8 TCs, if a packet with user priority 6 = or 7 is > injected to the NIC, then the NIC will put 3 packets into the queue. Ther= e's > also a similar issue for 4 TCs. > The root cause is RXPBSIZE is not right. RXPBSIZE of x550 is 384. It's di= fferent > from other 10G NICs. We need to set the RXPBSIZE according to the NIC typ= e. >=20 > Signed-off-by: Wenzhuo Lu Acked-by: Jingjing Wu > --- > drivers/net/ixgbe/ixgbe_rxtx.c | 27 +++++++++++++++++++++++---- > 1 file changed, 23 insertions(+), 4 deletions(-) >=20 > diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxt= x.c > index 91023b9..021229f 100644 > --- a/drivers/net/ixgbe/ixgbe_rxtx.c > +++ b/drivers/net/ixgbe/ixgbe_rxtx.c > @@ -2915,6 +2915,7 @@ ixgbe_rss_configure(struct rte_eth_dev *dev) >=20 > #define NUM_VFTA_REGISTERS 128 > #define NIC_RX_BUFFER_SIZE 0x200 > +#define X550_RX_BUFFER_SIZE 0x180 >=20 > static void > ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev) @@ -2943,7 +2944,15 > @@ ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev) > * RXPBSIZE > * split rx buffer up into sections, each for 1 traffic class > */ > - pbsize =3D (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs); > + switch (hw->mac.type) { > + case ixgbe_mac_X550: > + case ixgbe_mac_X550EM_x: > + pbsize =3D (uint16_t)(X550_RX_BUFFER_SIZE / nb_tcs); > + break; > + default: > + pbsize =3D (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs); > + break; > + } > for (i =3D 0 ; i < nb_tcs; i++) { > uint32_t rxpbsize =3D IXGBE_READ_REG(hw, > IXGBE_RXPBSIZE(i)); > rxpbsize &=3D (~(0x3FF << IXGBE_RXPBSIZE_SHIFT)); @@ - > 3317,7 +3326,7 @@ ixgbe_dcb_hw_configure(struct rte_eth_dev *dev, { > int ret =3D 0; > uint8_t i,pfc_en,nb_tcs; > - uint16_t pbsize; > + uint16_t pbsize, rx_buffer_size; > uint8_t config_dcb_rx =3D 0; > uint8_t config_dcb_tx =3D 0; > uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] =3D {0}; @@ -3408,9 > +3417,19 @@ ixgbe_dcb_hw_configure(struct rte_eth_dev *dev, > } > } >=20 > + switch (hw->mac.type) { > + case ixgbe_mac_X550: > + case ixgbe_mac_X550EM_x: > + rx_buffer_size =3D X550_RX_BUFFER_SIZE; > + break; > + default: > + rx_buffer_size =3D NIC_RX_BUFFER_SIZE; > + break; > + } > + > if(config_dcb_rx) { > /* Set RX buffer size */ > - pbsize =3D (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs); > + pbsize =3D (uint16_t)(rx_buffer_size / nb_tcs); > uint32_t rxpbsize =3D pbsize << IXGBE_RXPBSIZE_SHIFT; > for (i =3D 0 ; i < nb_tcs; i++) { > IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize); > @@ -3466,7 +3485,7 @@ ixgbe_dcb_hw_configure(struct rte_eth_dev *dev, >=20 > /* Check if the PFC is supported */ > if(dev->data->dev_conf.dcb_capability_en & > ETH_DCB_PFC_SUPPORT) { > - pbsize =3D (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs); > + pbsize =3D (uint16_t) (rx_buffer_size / nb_tcs); > for (i =3D 0; i < nb_tcs; i++) { > /* > * If the TC count is 8,and the default high_water is 48, > -- > 1.9.3