From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id D31148E7E for ; Mon, 19 Oct 2015 10:29:53 +0200 (CEST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga102.fm.intel.com with ESMTP; 19 Oct 2015 01:29:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,701,1437462000"; d="scan'208";a="796735934" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga001.jf.intel.com with ESMTP; 19 Oct 2015 01:29:52 -0700 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.248.2; Mon, 19 Oct 2015 01:29:52 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.194]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.204]) with mapi id 14.03.0248.002; Mon, 19 Oct 2015 16:29:50 +0800 From: "Wu, Jingjing" To: "Zhang, Helin" , "dev@dpdk.org" Thread-Topic: [PATCH 2/2] i40e: Enlarge the number of supported queues Thread-Index: AQHQ87PX+3xKYWvdqE2fnxV2Q4Dy9p5yqI4w Date: Mon, 19 Oct 2015 08:29:49 +0000 Message-ID: <9BB6961774997848B5B42BEC655768F8D035B4@SHSMSX104.ccr.corp.intel.com> References: <1442760674-19482-1-git-send-email-helin.zhang@intel.com> <1442760674-19482-3-git-send-email-helin.zhang@intel.com> In-Reply-To: <1442760674-19482-3-git-send-email-helin.zhang@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Cc: "Pei, Yulong" Subject: Re: [dpdk-dev] [PATCH 2/2] i40e: Enlarge the number of supported queues X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 19 Oct 2015 08:29:54 -0000 Hi, helin Few comments > a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index > 4b70588..3bdcaa4 100644 > --- a/drivers/net/i40e/i40e_ethdev.c > +++ b/drivers/net/i40e/i40e_ethdev.c > @@ -2240,113 +2240,88 @@ i40e_pf_parameter_init(struct rte_eth_dev > *dev) { > struct i40e_pf *pf =3D I40E_DEV_PRIVATE_TO_PF(dev->data- > >dev_private); > struct i40e_hw *hw =3D I40E_PF_TO_HW(pf); > - uint16_t sum_queues =3D 0, sum_vsis, left_queues; > + uint16_t qp_count =3D 0, vsi_count =3D 0; >=20 > - /* First check if FW support SRIOV */ > if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) { > PMD_INIT_LOG(ERR, "HW configuration doesn't support > SRIOV"); > return -EINVAL; > } >=20 > pf->flags =3D I40E_FLAG_HEADER_SPLIT_DISABLED; > - pf->max_num_vsi =3D RTE_MIN(hw->func_caps.num_vsis, > I40E_MAX_NUM_VSIS); > - PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi); > - /* Allocate queues for pf */ > - if (hw->func_caps.rss) { > - pf->flags |=3D I40E_FLAG_RSS; > - pf->lan_nb_qps =3D RTE_MIN(hw->func_caps.num_tx_qp, > - (uint32_t)(1 << hw- > >func_caps.rss_table_entry_width)); > - pf->lan_nb_qps =3D i40e_align_floor(pf->lan_nb_qps); > - } else > + pf->max_num_vsi =3D hw->func_caps.num_vsis; > + pf->lan_nb_qp_max =3D RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF; > + pf->vmdq_nb_qp_max =3D RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM; > + pf->vf_nb_qp_max =3D RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF; > + Need use the NUM_PER_VF but not NUM_PER_PF pf->vf_nb_qp_max =3D RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF=1B$B!(=1B(B =3D=3D> p= f->vf_nb_qp_max =3D RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;