From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id C66FA5A4E for ; Sun, 14 Feb 2016 03:12:33 +0100 (CET) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP; 13 Feb 2016 18:12:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,443,1449561600"; d="scan'208";a="651962289" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by FMSMGA003.fm.intel.com with ESMTP; 13 Feb 2016 18:12:32 -0800 Received: from FMSMSX110.amr.corp.intel.com (10.18.116.10) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.248.2; Sat, 13 Feb 2016 18:12:32 -0800 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by fmsmsx110.amr.corp.intel.com (10.18.116.10) with Microsoft SMTP Server (TLS) id 14.3.248.2; Sat, 13 Feb 2016 18:12:32 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.117]) by shsmsx102.ccr.corp.intel.com ([169.254.2.172]) with mapi id 14.03.0248.002; Sun, 14 Feb 2016 10:12:29 +0800 From: "Wu, Jingjing" To: "Tao, Zhe" Thread-Topic: [dpdk-dev] [PATCH v2 2/2] i40evf: support interrupt based pf reset request Thread-Index: AQHRWZn374dhiVeHZE2fEQK/rqq4oZ8q5j5w Date: Sun, 14 Feb 2016 02:12:29 +0000 Message-ID: <9BB6961774997848B5B42BEC655768F8D98AB2@SHSMSX104.ccr.corp.intel.com> References: <1452688307-20213-1-git-send-email-jingjing.wu@intel.com> <1453859378-23912-1-git-send-email-jingjing.wu@intel.com> <1453859378-23912-3-git-send-email-jingjing.wu@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Cc: "dev@dpdk.org" Subject: Re: [dpdk-dev] [PATCH v2 2/2] i40evf: support interrupt based pf reset request X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 14 Feb 2016 02:12:34 -0000 > -----Original Message----- > From: Tao, Zhe > Sent: Thursday, January 28, 2016 3:03 PM > To: Wu, Jingjing > Cc: dev@dpdk.org > Subject: RE: [dpdk-dev] [PATCH v2 2/2] i40evf: support interrupt based pf > reset request >=20 > > @@ -74,8 +74,6 @@ > > +static void > > @@ -1662,7 +1869,8 @@ (struct rte_eth_dev > > *dev) > > I40E_WRITE_REG(hw, > > I40E_VFINT_DYN_CTL01, > > I40E_VFINT_DYN_CTL01_INTENA_MASK | > > - I40E_VFINT_DYN_CTL01_CLEARPBA_MASK); > > + I40E_VFINT_DYN_CTL01_CLEARPBA_MASK | > > + I40E_VFINT_DYN_CTL01_ITR_INDX_MASK); > What the usage for ITR bits here? According to the access type of register I40E_VFINT_DYN_CTL01, the ITR_INDX= _MASK here means don't update the ITR index. > > I40EVF_WRITE_FLUSH(hw); > > return; > > }