From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id A5443952 for ; Sun, 14 Feb 2016 04:04:23 +0100 (CET) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP; 13 Feb 2016 19:04:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,443,1449561600"; d="scan'208";a="745649177" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by orsmga003.jf.intel.com with ESMTP; 13 Feb 2016 19:04:22 -0800 Received: from fmsmsx112.amr.corp.intel.com (10.18.116.6) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.248.2; Sat, 13 Feb 2016 19:04:22 -0800 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by FMSMSX112.amr.corp.intel.com (10.18.116.6) with Microsoft SMTP Server (TLS) id 14.3.248.2; Sat, 13 Feb 2016 19:04:21 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.117]) by shsmsx102.ccr.corp.intel.com ([169.254.2.172]) with mapi id 14.03.0248.002; Sun, 14 Feb 2016 11:04:20 +0800 From: "Wu, Jingjing" To: "Tao, Zhe" , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH v2 2/2] i40evf: support interrupt based pf reset request Thread-Index: AQHRWnIj124ekr1RIUOsjWl+cE9P+Z8q6B4g Date: Sun, 14 Feb 2016 03:04:19 +0000 Message-ID: <9BB6961774997848B5B42BEC655768F8D98B30@SHSMSX104.ccr.corp.intel.com> References: <1452688307-20213-1-git-send-email-jingjing.wu@intel.com> <1453859378-23912-1-git-send-email-jingjing.wu@intel.com> <1453859378-23912-3-git-send-email-jingjing.wu@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2 2/2] i40evf: support interrupt based pf reset request X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 14 Feb 2016 03:04:24 -0000 > -----Original Message----- > From: Tao, Zhe > Sent: Friday, January 29, 2016 4:51 PM > To: Wu, Jingjing; dev@dpdk.org > Subject: RE: [dpdk-dev] [PATCH v2 2/2] i40evf: support interrupt based pf > reset request >=20 >=20 >=20 > > -----Original Message----- > > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Jingjing Wu > > Sent: Wednesday, January 27, 2016 9:50 AM > > To: dev@dpdk.org > > Subject: [dpdk-dev] [PATCH v2 2/2] i40evf: support interrupt based pf > > reset request > > > > Interrupt based request of PF reset from PF is supported by enabling > > the adminq event process in VF driver. > > Users can register a callback for this interrupt event to get > > informed, when a PF reset request detected like: > > rte_eth_dev_callback_register(portid, > > RTE_ETH_EVENT_INTR_RESET, > > reset_event_callback, > > arg); > > > > Signed-off-by: Jingjing Wu > Two questions, > 1.If the VF RX/TX using msix 1 and Admin Queue using msix 0, how the two > interrupts can both be read in user spaces, in VM VFIO not supported, >=20 If i40e kernel driver is used as host driver, no matter VM VFIO is supporte= d or not, only msix 0 is reserved for DPDK i40e VF. > 2.But if we want to run l3fwd-power in VF, we can only assign the rx/tx = intr > to msix0, but both thread will using epoll to wait the msix0 event, and i= ntr > thread may miss the vf reset event if l3fwd-power thread clean the msix0 > related fd firstly if there are no more packets and msg response come in= , the > intr thread will not be wake up again Yes, you are right. The same as above answer, if i40e kernel driver is used= as host driver, then RX interrupt is not supported. Thanks Jingjing=20