From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D3377A04FD; Tue, 17 May 2022 09:56:25 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 85C2540042; Tue, 17 May 2022 09:56:25 +0200 (CEST) Received: from mailgw02.pantheon.sk (mailgw01.pantheon.sk [46.229.239.26]) by mails.dpdk.org (Postfix) with ESMTP id 0E3F340041 for ; Tue, 17 May 2022 09:56:24 +0200 (CEST) Received: from mailgw02.pantheon.sk (localhost.localdomain [127.0.0.1]) by mailgw02.pantheon.sk (Proxmox) with ESMTP id AEDCA182D67; Tue, 17 May 2022 09:56:23 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pantheon.tech; h=cc:cc:content-transfer-encoding:content-type:content-type :date:from:from:in-reply-to:message-id:mime-version:references :reply-to:subject:subject:to:to; s=dkim; bh=IZmSl/42VXCKU5uRPpN3 Uus0finPIqMz+Yprir7PLSA=; b=hJdER3g4yr+y5nmi12UFKMh8GHVyK89CKATl i9Kf6VHuTjokikmlcfQkBVUZt/dvJEf0jh0HDPZBl7UN8KkSiQvVpskUCXQYc70R 4DnlktCn/9xBrHiz8xVN2fttR2a12LBRl+oMgMnEdBQMm4vVyhbhz//t5lWfqoRS Sg7TvMdiR1YTQnBaaNPwDvV2cjaN07eIqitK37Ursr0T3YfOin5VsAZiSX2g4NtV IrK9fbaHmmYV6ByKA4yLjPXsc99vdtkPCiaUsBAFf7eijcVLOsxoKr/3dJaKl+44 tqdVjrELjIStwtQbkE2xdlXyqymVX1AvQLeJXpjh3BTB8qV/Sw== From: =?iso-8859-2?Q?Juraj_Linke=B9?= To: Rahul Bhansali , "dev@dpdk.org" , Ruifeng Wang , Jan Viktorin , Bruce Richardson CC: "jerinj@marvell.com" Subject: RE: [PATCH v4 1/2] config/arm: add SVE ACLE control flag Thread-Topic: [PATCH v4 1/2] config/arm: add SVE ACLE control flag Thread-Index: AQHYY45XK2ONfH1ELEyeiEhP4KDILK0hj6qg Date: Tue, 17 May 2022 07:56:21 +0000 Message-ID: <9c1c547ea2c24bcb8c058b70ccbfe026@pantheon.tech> References: <20220505142744.1423344-1-rbhansali@marvell.com> <20220509101932.2403562-1-rbhansali@marvell.com> In-Reply-To: <20220509101932.2403562-1-rbhansali@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.101.4.10] Content-Type: text/plain; charset="iso-8859-2" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > -----Original Message----- > From: Rahul Bhansali > Sent: Monday, May 9, 2022 12:20 PM > To: dev@dpdk.org; Ruifeng Wang ; Jan Viktorin > ; Bruce Richardson > Cc: jerinj@marvell.com; Rahul Bhansali > Subject: [PATCH v4 1/2] config/arm: add SVE ACLE control flag >=20 > This add the control flag for SVE ACLE to enable or disable RTE_HAS_SVE_A= CLE > macro in the build. >=20 > Signed-off-by: Rahul Bhansali > --- > Changes in v4: > - Resend patches. With v3, patches were not sent properly in single serie= s. >=20 > Changes in v3: > - Moved sve_acle condition to be consider for RTE_HAS_SVE_ACLE flag only. >=20 > Changes in v2: > - Renamed the flag to sve_acle from sve > - Added double-indent. >=20 > config/arm/meson.build | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/config/arm/meson.build b/config/arm/meson.build index > 8aead74086..6f8961eac8 100644 > --- a/config/arm/meson.build > +++ b/config/arm/meson.build > @@ -605,7 +605,7 @@ endif >=20 > if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) !=3D '' > compile_time_cpuflags +=3D ['RTE_CPUFLAG_SVE'] > - if (cc.check_header('arm_sve.h')) > + if (cc.check_header('arm_sve.h') and soc_config.get('sve_acle', > + true)) This configuration will be applied only for non-native builds - when we spe= cify either -Dplatform or do a cross-build (with the target being cn10k). I= s that what we want? I'm not sure how we'd do that for native builds that w= on't affect non-cn10k builds, as we can do this either at the implementer o= r part number level (both of which cover other SoCs). > dpdk_conf.set('RTE_HAS_SVE_ACLE', 1) > endif > endif > -- > 2.25.1 >=20