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d="scan'208";a="449484622" Received: from fmsmsx601.amr.corp.intel.com ([10.18.126.81]) by orsmga004.jf.intel.com with ESMTP; 09 Sep 2020 23:45:51 -0700 Received: from shsmsx604.ccr.corp.intel.com (10.109.6.214) by fmsmsx601.amr.corp.intel.com (10.18.126.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 9 Sep 2020 23:45:50 -0700 Received: from shsmsx603.ccr.corp.intel.com (10.109.6.143) by SHSMSX604.ccr.corp.intel.com (10.109.6.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Thu, 10 Sep 2020 14:45:48 +0800 Received: from shsmsx603.ccr.corp.intel.com ([10.109.6.143]) by SHSMSX603.ccr.corp.intel.com ([10.109.6.143]) with mapi id 15.01.1713.004; Thu, 10 Sep 2020 14:45:48 +0800 From: "Jiang, JunyuX" To: "Guo, Jia" , "Han, YingyaX" , "dev@dpdk.org" CC: "Xing, Beilei" , "stable@dpdk.org" Thread-Topic: [dpdk-stable] [PATCH] net/i40e: fix incorrect byte counters Thread-Index: AQHWhxaiEw8GXZIDikyS6uJTEztz/algnQmAgAA9gACAAJL4wA== Date: Thu, 10 Sep 2020 06:45:48 +0000 Message-ID: <9e9d954ecf924b4da0d0d72484a5f9e5@intel.com> References: <20200910015426.3140-1-junyux.jiang@intel.com> <2c0b8b4ff5ce41d6868c5889e5a0c379@intel.com> In-Reply-To: <2c0b8b4ff5ce41d6868c5889e5a0c379@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [dpdk-stable] [PATCH] net/i40e: fix incorrect byte counters X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" HI guojia, > -----Original Message----- > From: Guo, Jia > Sent: Thursday, September 10, 2020 1:59 PM > To: Han, YingyaX ; Jiang, JunyuX > ; dev@dpdk.org > Cc: Xing, Beilei ; Jiang, JunyuX > ; stable@dpdk.org > Subject: RE: [dpdk-stable] [PATCH] net/i40e: fix incorrect byte counters >=20 > Hi, junyu >=20 > > -----Original Message----- > > From: Han, YingyaX > > Sent: Thursday, September 10, 2020 10:18 AM > > To: Jiang, JunyuX ; dev@dpdk.org > > Cc: Guo, Jia ; Xing, Beilei > > ; Jiang, JunyuX ; > > stable@dpdk.org > > Subject: RE: [dpdk-stable] [PATCH] net/i40e: fix incorrect byte > > counters > > > > Tested-by: Yingya Han > > > > -----Original Message----- > > From: stable On Behalf Of Junyu Jiang > > Sent: Thursday, September 10, 2020 9:54 AM > > To: dev@dpdk.org > > Cc: Guo, Jia ; Xing, Beilei > > ; Jiang, JunyuX ; > > stable@dpdk.org > > Subject: [dpdk-stable] [PATCH] net/i40e: fix incorrect byte counters > > > > This patch fixed the issue that rx/tx bytes overflowed on 48 bit > > limitation by enlarging the limitation. > > > > Fixes: 4861cde46116 ("i40e: new poll mode driver") > > Cc: stable@dpdk.org > > > > Signed-off-by: Junyu Jiang > > --- > > drivers/net/i40e/i40e_ethdev.c | 47 > > ++++++++++++++++++++++++++++++++++ > > drivers/net/i40e/i40e_ethdev.h | 9 +++++++ > > 2 files changed, 56 insertions(+) > > > > diff --git a/drivers/net/i40e/i40e_ethdev.c > > b/drivers/net/i40e/i40e_ethdev.c index 11c02b188..e3d4b7f4f 100644 > > --- a/drivers/net/i40e/i40e_ethdev.c > > +++ b/drivers/net/i40e/i40e_ethdev.c > > @@ -3070,6 +3070,13 @@ i40e_update_vsi_stats(struct i40e_vsi *vsi) > > i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx), > > vsi->offset_loaded, &oes->rx_broadcast, > > &nes->rx_broadcast); > > +/* enlarge the limitation when rx_bytes overflowed */ if > > +(vsi->offset_loaded) { if (I40E_RXTX_BYTES_LOW(vsi->old_rx_bytes) > > > +nes->rx_bytes) > > +nes->rx_bytes +=3D (uint64_t)1 << I40E_48_BIT_WIDTH; rx_bytes +=3D > > +nes->I40E_RXTX_BYTES_HIGH(vsi->old_rx_bytes); > > +} > > +vsi->old_rx_bytes =3D nes->rx_bytes; > > /* exclude CRC bytes */ > > nes->rx_bytes -=3D (nes->rx_unicast + nes->rx_multicast + > > nes->rx_broadcast) * RTE_ETHER_CRC_LEN; @@ -3096,6 +3103,13 @@ > > i40e_update_vsi_stats(struct i40e_vsi *vsi) > > /* GLV_TDPC not supported */ > > i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded, > > &oes->tx_errors, &nes->tx_errors); > > +/* enlarge the limitation when tx_bytes overflowed */ if > > +(vsi->offset_loaded) { if (I40E_RXTX_BYTES_LOW(vsi->old_tx_bytes) > > > +nes->tx_bytes) > > +nes->tx_bytes +=3D (uint64_t)1 << I40E_48_BIT_WIDTH; tx_bytes +=3D > > +nes->I40E_RXTX_BYTES_HIGH(vsi->old_tx_bytes); > > +} > > +vsi->old_rx_bytes =3D nes->rx_bytes; >=20 > It should be tx, right? >=20 You are right, it will be fixed in V2. > > vsi->offset_loaded =3D true; > >