From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id 9F53B1EB19; Thu, 14 Jun 2018 03:52:14 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Jun 2018 18:52:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,220,1526367600"; d="scan'208";a="237287650" Received: from pgsmsx105.gar.corp.intel.com ([10.221.44.96]) by fmsmga006.fm.intel.com with ESMTP; 13 Jun 2018 18:52:11 -0700 Received: from pgsmsx103.gar.corp.intel.com ([169.254.2.131]) by PGSMSX105.gar.corp.intel.com ([169.254.4.136]) with mapi id 14.03.0319.002; Thu, 14 Jun 2018 09:52:10 +0800 From: "Zhao1, Wei" To: "Lu, Wenzhuo" , "dev@dpdk.org" CC: "stable@dpdk.org" Thread-Topic: [PATCH] net/ixgbe: fix mask bits register set error for FDIR Thread-Index: AQHUAvEiaotErM18jEm5N5pZUU0bzKReZ/UAgACWglA= Date: Thu, 14 Jun 2018 01:52:10 +0000 Message-ID: References: <1528877530-5133-1-git-send-email-wei.zhao1@intel.com> <6A0DE07E22DDAD4C9103DF62FEBC09093B7E8F6B@shsmsx102.ccr.corp.intel.com> In-Reply-To: <6A0DE07E22DDAD4C9103DF62FEBC09093B7E8F6B@shsmsx102.ccr.corp.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.200.100 dlp-reaction: no-action x-originating-ip: [172.30.20.206] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] net/ixgbe: fix mask bits register set error for FDIR X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jun 2018 01:52:16 -0000 Hi, wenzhuo > -----Original Message----- > From: Lu, Wenzhuo > Sent: Thursday, June 14, 2018 8:53 AM > To: Zhao1, Wei ; dev@dpdk.org > Cc: stable@dpdk.org > Subject: RE: [PATCH] net/ixgbe: fix mask bits register set error for FDIR >=20 > Hi Wei, >=20 > > -----Original Message----- > > From: Zhao1, Wei > > Sent: Wednesday, June 13, 2018 4:12 PM > > To: dev@dpdk.org > > Cc: Lu, Wenzhuo ; stable@dpdk.org; Zhao1, Wei > > > > Subject: [PATCH] net/ixgbe: fix mask bits register set error for FDIR > > > > MAC address bits in mask registers should be set to zero when the is > > mac mask is 0xFF, otherwise if it is 0x0 these bits should be to 0x3F. > > > > Fixes: 82fb702077f6 ("ixgbe: support new flow director modes for > > X550") > > > > Signed-off-by: Wei Zhao > > --- > > drivers/net/ixgbe/ixgbe_fdir.c | 12 +++++++++--- > > 1 file changed, 9 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/net/ixgbe/ixgbe_fdir.c > > b/drivers/net/ixgbe/ixgbe_fdir.c index 3feb815..6d97aa3 100644 > > --- a/drivers/net/ixgbe/ixgbe_fdir.c > > +++ b/drivers/net/ixgbe/ixgbe_fdir.c > > @@ -394,9 +394,15 @@ fdir_set_input_mask_x550(struct rte_eth_dev > *dev) > > IXGBE_FDIRIP6M_TNI_VNI; > > > > if (mode =3D=3D RTE_FDIR_MODE_PERFECT_TUNNEL) { > > - mac_mask =3D info->mask.mac_addr_byte_mask; > > - fdiripv6m |=3D (mac_mask << > > IXGBE_FDIRIP6M_INNER_MAC_SHIFT) > > - & IXGBE_FDIRIP6M_INNER_MAC; > > + mac_mask =3D info->mask.mac_addr_byte_mask & 0x3F; > Better not use 0x3f, you can change it to "IXGBE_FDIRIP6M_INNER_MAC >> > IXGBE_FDIRIP6M_INNER_MAC_SHIFT" >=20 > > + if (mac_mask =3D=3D 0x3F) > > + fdiripv6m &=3D ~IXGBE_FDIRIP6M_INNER_MAC; > > + else if (mac_mask =3D=3D 0) > > + fdiripv6m |=3D IXGBE_FDIRIP6M_INNER_MAC; > > + else{ > > + PMD_INIT_LOG(ERR, "invalid > mac_addr_byte_mask"); > > + return -EINVAL; > I think every byte of the MAC address can be masked. So this is not the > invalid case. We should support 0x1f, 0xf, 0x7... as before. Ok, I will commit v3 >=20 > > + } > > > > switch (info->mask.tunnel_type_mask) { > > case 0: > > -- > > 2.7.5