From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id 243AA2BD5 for ; Tue, 20 Nov 2018 04:29:28 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Nov 2018 19:29:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,255,1539673200"; d="scan'208";a="109694095" Received: from pgsmsx103.gar.corp.intel.com ([10.221.44.82]) by orsmga001.jf.intel.com with ESMTP; 19 Nov 2018 19:29:26 -0800 Received: from pgsmsx101.gar.corp.intel.com ([169.254.1.244]) by PGSMSX103.gar.corp.intel.com ([169.254.2.155]) with mapi id 14.03.0415.000; Tue, 20 Nov 2018 11:29:25 +0800 From: "Zhao1, Wei" To: "Player, Timmons" CC: "dev@dpdk.org" , "Lu, Wenzhuo" Thread-Topic: [PATCH v2] net/igb: fix LSC interrupt when using MSI-X Thread-Index: AQHUgBb+/9QoQxnqWE2foIYOgJptGqVYAjLg Date: Tue, 20 Nov 2018 03:29:25 +0000 Message-ID: References: <20181119144833.7732-1-timmons.player@spirent.com> In-Reply-To: <20181119144833.7732-1-timmons.player@spirent.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [172.30.20.205] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2] net/igb: fix LSC interrupt when using MSI-X X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 20 Nov 2018 03:29:30 -0000 Acked-by: Wei Zhao > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Player, Timmons > Sent: Monday, November 19, 2018 10:49 PM > To: Lu, Wenzhuo > Cc: dev@dpdk.org; Player, Timmons > Subject: [dpdk-dev] [PATCH v2] net/igb: fix LSC interrupt when using MSI-= X >=20 > Take the 'other interrupt' into account when setting up MSI-X interrupts = and > use the proper mask when enabling it. > Also, rearm the MSI-X vector after the LSC interrupt fires. >=20 > This change allows both LSC and RXQ interrupts to work at the same time > when using MSI-X interrupts. >=20 > Signed-off-by: Timmons C. Player > --- > v2: > * Update igb_intr_{enable,disable} to only touch the 'other interrupt' > when it is explicitly enabled. >=20 > drivers/net/e1000/igb_ethdev.c | 43 +++++++++++++++++++++++++++++- > ---- > 1 file changed, 37 insertions(+), 6 deletions(-) >=20 > diff --git a/drivers/net/e1000/igb_ethdev.c > b/drivers/net/e1000/igb_ethdev.c index d9d29d22f..87c9aedf2 100644 > --- a/drivers/net/e1000/igb_ethdev.c > +++ b/drivers/net/e1000/igb_ethdev.c > @@ -68,6 +68,9 @@ > #define E1000_VET_VET_EXT 0xFFFF0000 > #define E1000_VET_VET_EXT_SHIFT 16 >=20 > +/* MSI-X other interrupt vector */ > +#define IGB_MSIX_OTHER_INTR_VEC 0 > + > static int eth_igb_configure(struct rte_eth_dev *dev); static int > eth_igb_start(struct rte_eth_dev *dev); static void eth_igb_stop(struct > rte_eth_dev *dev); @@ -138,7 +141,7 @@ static void > igb_vlan_hw_extend_disable(struct rte_eth_dev *dev); static int > eth_igb_led_on(struct rte_eth_dev *dev); static int eth_igb_led_off(stru= ct > rte_eth_dev *dev); >=20 > -static void igb_intr_disable(struct e1000_hw *hw); > +static void igb_intr_disable(struct rte_eth_dev *dev); > static int igb_get_rx_buffer_size(struct e1000_hw *hw); static int > eth_igb_rar_set(struct rte_eth_dev *dev, > struct ether_addr *mac_addr, > @@ -538,14 +541,31 @@ igb_intr_enable(struct rte_eth_dev *dev) > E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private); > struct e1000_hw *hw =3D > E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); > + struct rte_pci_device *pci_dev =3D RTE_ETH_DEV_TO_PCI(dev); > + struct rte_intr_handle *intr_handle =3D &pci_dev->intr_handle; > + > + if (rte_intr_allow_others(intr_handle) && > + dev->data->dev_conf.intr_conf.lsc !=3D 0) { > + E1000_WRITE_REG(hw, E1000_EIMS, 1 << > IGB_MSIX_OTHER_INTR_VEC); > + } >=20 > E1000_WRITE_REG(hw, E1000_IMS, intr->mask); > E1000_WRITE_FLUSH(hw); > } >=20 > static void > -igb_intr_disable(struct e1000_hw *hw) > +igb_intr_disable(struct rte_eth_dev *dev) > { > + struct e1000_hw *hw =3D > + E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); > + struct rte_pci_device *pci_dev =3D RTE_ETH_DEV_TO_PCI(dev); > + struct rte_intr_handle *intr_handle =3D &pci_dev->intr_handle; > + > + if (rte_intr_allow_others(intr_handle) && > + dev->data->dev_conf.intr_conf.lsc !=3D 0) { > + E1000_WRITE_REG(hw, E1000_EIMC, 1 << > IGB_MSIX_OTHER_INTR_VEC); > + } > + > E1000_WRITE_REG(hw, E1000_IMC, ~0); > E1000_WRITE_FLUSH(hw); > } > @@ -1486,7 +1506,7 @@ eth_igb_stop(struct rte_eth_dev *dev) >=20 > eth_igb_rxtx_control(dev, false); >=20 > - igb_intr_disable(hw); > + igb_intr_disable(dev); >=20 > /* disable intr eventfd mapping */ > rte_intr_disable(intr_handle); > @@ -2768,12 +2788,15 @@ static int eth_igb_rxq_interrupt_setup(struct > rte_eth_dev *dev) > uint32_t mask, regval; > struct e1000_hw *hw =3D > E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); > + struct rte_pci_device *pci_dev =3D RTE_ETH_DEV_TO_PCI(dev); > + struct rte_intr_handle *intr_handle =3D &pci_dev->intr_handle; > + int misc_shift =3D rte_intr_allow_others(intr_handle) ? 1 : 0; > struct rte_eth_dev_info dev_info; >=20 > memset(&dev_info, 0, sizeof(dev_info)); > eth_igb_infos_get(dev, &dev_info); >=20 > - mask =3D 0xFFFFFFFF >> (32 - dev_info.max_rx_queues); > + mask =3D (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << > misc_shift; > regval =3D E1000_READ_REG(hw, E1000_EIMS); > E1000_WRITE_REG(hw, E1000_EIMS, regval | mask); >=20 > @@ -2800,7 +2823,7 @@ eth_igb_interrupt_get_status(struct rte_eth_dev > *dev) > struct e1000_interrupt *intr =3D > E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private); >=20 > - igb_intr_disable(hw); > + igb_intr_disable(dev); >=20 > /* read-on-clear nic registers here */ > icr =3D E1000_READ_REG(hw, E1000_ICR); > @@ -5583,13 +5606,17 @@ eth_igb_configure_msix_intr(struct rte_eth_dev > *dev) > E1000_GPIE_NSICR); > intr_mask =3D RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) > << > misc_shift; > + > + if (dev->data->dev_conf.intr_conf.lsc !=3D 0) > + intr_mask |=3D (1 << IGB_MSIX_OTHER_INTR_VEC); > + > regval =3D E1000_READ_REG(hw, E1000_EIAC); > E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask); >=20 > /* enable msix_other interrupt */ > regval =3D E1000_READ_REG(hw, E1000_EIMS); > E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask); > - tmpval =3D (dev->data->nb_rx_queues | E1000_IVAR_VALID) > << 8; > + tmpval =3D (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) > << 8; > E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval); > } >=20 > @@ -5598,6 +5625,10 @@ eth_igb_configure_msix_intr(struct rte_eth_dev > *dev) > */ > intr_mask =3D RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) << > misc_shift; > + > + if (dev->data->dev_conf.intr_conf.lsc !=3D 0) > + intr_mask |=3D (1 << IGB_MSIX_OTHER_INTR_VEC); > + > regval =3D E1000_READ_REG(hw, E1000_EIAM); > E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask); >=20 > -- > 2.17.1