From: Yongseok Koh <yskoh@mellanox.com>
To: Shahaf Shuler <shahafs@mellanox.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>
Subject: Re: [dpdk-dev] [PATCH 1/2] net/mlx5: fix bit width of flow items
Date: Fri, 26 Oct 2018 23:01:19 +0000 [thread overview]
Message-ID: <A5663B9D-C0E9-4364-BC71-BC3FCA7F2DF1@mellanox.com> (raw)
In-Reply-To: <20181025085351.15738-1-shahafs@mellanox.com>
> On Oct 25, 2018, at 1:53 AM, Shahaf Shuler <shahafs@mellanox.com> wrote:
>
> Apply the changes from commit c744f6b1b969 ("net/mlx5: fix bit width of
> item and action flags") in some places that were overlooked.
>
> Fixes: c744f6b1b969 ("net/mlx5: fix bit width of item and action flags")
> Fixes: 23c1d42c7138 ("net/mlx5: split flow validation to dedicated function")
>
> Signed-off-by: Shahaf Shuler <shahafs@mellanox.com>
> ---
Acked-by: Yongseok Koh <yskoh@mellanox.com>
Thanks
> drivers/net/mlx5/mlx5_flow.c | 10 +++++-----
> drivers/net/mlx5/mlx5_flow.h | 4 ++--
> 2 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
> index 280af0abce..87189a3405 100644
> --- a/drivers/net/mlx5/mlx5_flow.c
> +++ b/drivers/net/mlx5/mlx5_flow.c
> @@ -275,7 +275,7 @@ static const uint32_t priority_map_5[][MLX5_PRIORITY_MAP_MAX] = {
>
> /* Tunnel information. */
> struct mlx5_flow_tunnel_info {
> - uint32_t tunnel; /**< Tunnel bit (see MLX5_FLOW_*). */
> + uint64_t tunnel; /**< Tunnel bit (see MLX5_FLOW_*). */
> uint32_t ptype; /**< Tunnel Ptype (see RTE_PTYPE_*). */
> };
>
> @@ -1079,7 +1079,7 @@ mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
> */
> int
> mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
> - int64_t item_flags,
> + uint64_t item_flags,
> struct rte_flow_error *error)
> {
> const struct rte_flow_item_vlan *spec = item->spec;
> @@ -1091,11 +1091,11 @@ mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
> uint16_t vlan_tag = 0;
> const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
> int ret;
> - const uint32_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
> + const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
> MLX5_FLOW_LAYER_INNER_L4) :
> (MLX5_FLOW_LAYER_OUTER_L3 |
> MLX5_FLOW_LAYER_OUTER_L4);
> - const uint32_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
> + const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
> MLX5_FLOW_LAYER_OUTER_VLAN;
>
> if (item_flags & vlanm)
> @@ -1145,7 +1145,7 @@ mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
> */
> int
> mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
> - int64_t item_flags,
> + uint64_t item_flags,
> struct rte_flow_error *error)
> {
> const struct rte_flow_item_ipv4 *mask = item->mask;
> diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
> index 61299d66b3..c24d26ed45 100644
> --- a/drivers/net/mlx5/mlx5_flow.h
> +++ b/drivers/net/mlx5/mlx5_flow.h
> @@ -336,7 +336,7 @@ int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
> uint8_t target_protocol,
> struct rte_flow_error *error);
> int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
> - int64_t item_flags,
> + uint64_t item_flags,
> struct rte_flow_error *error);
> int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
> uint64_t item_flags,
> @@ -355,7 +355,7 @@ int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
> uint8_t target_protocol,
> struct rte_flow_error *error);
> int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
> - int64_t item_flags,
> + uint64_t item_flags,
> struct rte_flow_error *error);
> int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
> uint64_t item_flags,
> --
> 2.12.0
>
next prev parent reply other threads:[~2018-10-26 23:01 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-25 8:53 Shahaf Shuler
2018-10-25 8:53 ` [dpdk-dev] [PATCH 2/2] net/mlx5: fix detection and error for multiple item layers Shahaf Shuler
2018-10-26 23:01 ` Yongseok Koh
2018-10-26 23:01 ` Yongseok Koh [this message]
2018-10-28 12:53 ` [dpdk-dev] [PATCH 1/2] net/mlx5: fix bit width of flow items Shahaf Shuler
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