From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id 7F5325938 for ; Sat, 13 Feb 2016 11:18:22 +0100 (CET) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP; 13 Feb 2016 02:18:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,439,1449561600"; d="scan'208";a="902081843" Received: from irsmsx110.ger.corp.intel.com ([163.33.3.25]) by fmsmga001.fm.intel.com with ESMTP; 13 Feb 2016 02:18:20 -0800 Received: from irsmsx106.ger.corp.intel.com ([169.254.8.197]) by irsmsx110.ger.corp.intel.com ([169.254.15.31]) with mapi id 14.03.0248.002; Sat, 13 Feb 2016 10:18:19 +0000 From: "Chilikin, Andrey" To: "dev@dpdk.org" Thread-Topic: [PATCH] i40e: fix for default flexible payload registers settings Thread-Index: AQHQ+2CsDk3oOx8/CkGpNY20WwT9P58qlsOA Date: Sat, 13 Feb 2016 10:18:19 +0000 Message-ID: References: <1443604567-24875-1-git-send-email-andrey.chilikin@intel.com> In-Reply-To: <1443604567-24875-1-git-send-email-andrey.chilikin@intel.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.180] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] i40e: fix for default flexible payload registers settings X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 13 Feb 2016 10:18:22 -0000 > -----Original Message----- > From: Chilikin, Andrey > Sent: Wednesday, September 30, 2015 10:16 AM > To: dev@dpdk.org > Cc: Chilikin, Andrey > Subject: [PATCH] i40e: fix for default flexible payload registers setting= s >=20 > This patch applies new default values to flexible payload configuration f= or flow > director filter >=20 > Signed-off-by: Andrey Chilikin > --- Self NAK. With the current default registers settings FVL handles all use c= ases the same way as with the new proposed configuration.