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Sun, 24 Mar 2019 06:37:42 +0000 From: Shahaf Shuler To: "pradeep@us.ibm.com" , Thomas Monjalon CC: "bruce.richardson@intel.com" , Chao Zhu , Dekel Peled , "dev@dpdk.org" , David Christensen , "honnappa.nagarahalli@arm.com" , "konstantin.ananyev@intel.com" , "ola.liljedahl@arm.com" , Ori Kam , David Wilder , Yongseok Koh Thread-Topic: [PATCH] eal/ppc: remove fix of memory barrier for IBM POWER Thread-Index: AQHU3js5UXrzwqXJNk26I7vX4kWVFKYSzYSAgACJ6eCAABVbgIABsqAAgACpvJCAARrtAIAAd6uAgABwOwCAACdFgIAAVZaAgAIR9uA= Date: Sun, 24 Mar 2019 06:37:42 +0000 Message-ID: References: <1552913893-43407-1-git-send-email-dekelp@mellanox.com> <11283309.AIL3tCH6tf@xps> <4334064.10fvSv6A2r@xps> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=shahafs@mellanox.com; x-originating-ip: [31.154.10.105] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 92526c50-b29b-4781-66e8-08d6b02337b4 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.15 Subject: Re: [dpdk-dev] [PATCH] eal/ppc: remove fix of memory barrier for IBM POWER X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 24 Mar 2019 06:37:45 -0000 Pradeep, Pradeep Satyanarayana wrote on Saturday, March 23, 2019 12:58 AM >Thomas Monjalon wrote on 03/22/2019 10:51:17 AM: >> Date: 03/22/2019 10:51 AM >> Subject: Re: [PATCH] eal/ppc: remove fix of memory barrier for IBM POWER >> >> 22/03/2019 16:30, Pradeep Satyanarayana: >> > Thomas Monjalon wrote on 03/22/2019 01:49:03 AM: >> > > 22/03/2019 02:40, Pradeep Satyanarayana: >> > > > - rte_[rw]mb (general memory barrier) --> should be lwsync >> > > >> > > This is what may be discussed. >> > > The assumption is that the general memory barrier should cover >> > > all cases (CPU caches, SMP and I/O). >> > > That's why we think it should "sync" for Power. >> > >> > In that case, at a minimum we must de-link rte_smp_[rw]mb from rte_[rw= ]mb >> > and retain it as lwsync. Agreed? >> >> I have no clue about what is needed for SMP barrier in Power. >> As long as it works as expected, no problem. >> > >We will try that out and report back here, later next week Till then, i think there are 2 orthogonal issues: 1. ppc rte_wmb is incorrect 2. ppc rte_smp_[rw]mb may be improved. for #1 the current patch from Dekel seems to be OK. do you agree? for #2 i guess you will check and come back w/ patch/answer? From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id CAF7AA05D3 for ; Sun, 24 Mar 2019 07:37:47 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 567F01B725; Sun, 24 Mar 2019 07:37:46 +0100 (CET) Received: from EUR03-VE1-obe.outbound.protection.outlook.com (mail-eopbgr50088.outbound.protection.outlook.com [40.107.5.88]) by dpdk.org (Postfix) with ESMTP id 593821B60F for ; Sun, 24 Mar 2019 07:37:45 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Mellanox.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=aSuKb0Q/rITbT6sdeI2ilToOVXPM9ihJ2Ju7+qlpAU0=; b=eCh/8LPlJ5ysS3VfMrVH/JuEXr+LTyZiRHC3dQVpP65T3p48ekIl7F8Y/NgBq0O6bYdUMf5DSbOYdZOlW9X8LnXhblsmBjbsMrnPGIEvpX/mLGUU/SIMNzyt01aJFfP1POlEiF23keP72U0ngSlSEhXPlAf97z3FAQiwqHqMRdE= Received: from AM0PR0502MB3795.eurprd05.prod.outlook.com (52.133.45.150) by AM0PR0502MB3762.eurprd05.prod.outlook.com (52.133.45.159) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1709.15; Sun, 24 Mar 2019 06:37:42 +0000 Received: from AM0PR0502MB3795.eurprd05.prod.outlook.com ([fe80::84f3:7e92:7a51:1003]) by AM0PR0502MB3795.eurprd05.prod.outlook.com ([fe80::84f3:7e92:7a51:1003%2]) with mapi id 15.20.1730.019; Sun, 24 Mar 2019 06:37:42 +0000 From: Shahaf Shuler To: "pradeep@us.ibm.com" , Thomas Monjalon CC: "bruce.richardson@intel.com" , Chao Zhu , Dekel Peled , "dev@dpdk.org" , David Christensen , "honnappa.nagarahalli@arm.com" , "konstantin.ananyev@intel.com" , "ola.liljedahl@arm.com" , Ori Kam , David Wilder , Yongseok Koh Thread-Topic: [PATCH] eal/ppc: remove fix of memory barrier for IBM POWER Thread-Index: AQHU3js5UXrzwqXJNk26I7vX4kWVFKYSzYSAgACJ6eCAABVbgIABsqAAgACpvJCAARrtAIAAd6uAgABwOwCAACdFgIAAVZaAgAIR9uA= Date: Sun, 24 Mar 2019 06:37:42 +0000 Message-ID: References: <1552913893-43407-1-git-send-email-dekelp@mellanox.com> <11283309.AIL3tCH6tf@xps> <4334064.10fvSv6A2r@xps> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=shahafs@mellanox.com; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.15 Subject: Re: [dpdk-dev] [PATCH] eal/ppc: remove fix of memory barrier for IBM POWER X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190324063742.mwtUScr0fg8s8XJfZ8GIHbQf0BsAS5EsMw7RW9_osTA@z> Pradeep, Pradeep Satyanarayana wrote on Saturday, March 23, 2019 12:58 AM >Thomas Monjalon wrote on 03/22/2019 10:51:17 AM: >> Date: 03/22/2019 10:51 AM >> Subject: Re: [PATCH] eal/ppc: remove fix of memory barrier for IBM POWER >> >> 22/03/2019 16:30, Pradeep Satyanarayana: >> > Thomas Monjalon wrote on 03/22/2019 01:49:03 AM: >> > > 22/03/2019 02:40, Pradeep Satyanarayana: >> > > > - rte_[rw]mb (general memory barrier) --> should be lwsync >> > > >> > > This is what may be discussed. >> > > The assumption is that the general memory barrier should cover >> > > all cases (CPU caches, SMP and I/O). >> > > That's why we think it should "sync" for Power. >> > >> > In that case, at a minimum we must de-link rte_smp_[rw]mb from rte_[rw= ]mb >> > and retain it as lwsync. Agreed? >> >> I have no clue about what is needed for SMP barrier in Power. >> As long as it works as expected, no problem. >> > >We will try that out and report back here, later next week Till then, i think there are 2 orthogonal issues: 1. ppc rte_wmb is incorrect 2. ppc rte_smp_[rw]mb may be improved. for #1 the current patch from Dekel seems to be OK. do you agree? for #2 i guess you will check and come back w/ patch/answer?