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Sun, 2 Feb 2020 13:22:35 +0000 Received: from AM0PR05MB6707.eurprd05.prod.outlook.com ([fe80::bdb0:493e:2231:1c8a]) by AM0PR05MB6707.eurprd05.prod.outlook.com ([fe80::bdb0:493e:2231:1c8a%3]) with mapi id 15.20.2686.031; Sun, 2 Feb 2020 13:22:35 +0000 From: Raslan Darawsheh To: Raslan Darawsheh , Slava Ovsiienko , Matan Azrad CC: "dev@dpdk.org" , Ori Kam , "stable@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH] net/mlx5: fix vxlan-gpe item translation Thread-Index: AQHV2aj5ijGmdkBLokmcE2iK1WeErqgH5FZg Date: Sun, 2 Feb 2020 13:22:35 +0000 Message-ID: References: <1580634775-645-1-git-send-email-rasland@mellanox.com> In-Reply-To: <1580634775-645-1-git-send-email-rasland@mellanox.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=rasland@mellanox.com; x-originating-ip: [212.29.221.74] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: e6eb1c85-a425-40d5-63b8-08d7a7e2f7a6 x-ms-traffictypediagnostic: AM0PR05MB5171:|AM0PR05MB5171: x-ld-processed: a652971c-7d2e-4d9b-a6a4-d149256f461b,ExtFwd x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:983; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: e6eb1c85-a425-40d5-63b8-08d7a7e2f7a6 X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Feb 2020 13:22:35.3428 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: tRK8lR8MGV8Asb/8r3hwaUEfa3ahfuTnRYTNT7XVK02wGmedIxWARXUUjYrZom1cjXzbQfTfh0P/POok53eA+g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR05MB5171 Subject: Re: [dpdk-dev] [PATCH] net/mlx5: fix vxlan-gpe item translation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi, > -----Original Message----- > From: dev On Behalf Of Raslan Darawsheh > Sent: Sunday, February 2, 2020 11:13 AM > To: slava@monjalon.net; Matan Azrad > Cc: dev@dpdk.org; Ori Kam ; stable@dpdk.org > Subject: [dpdk-dev] [PATCH] net/mlx5: fix vxlan-gpe item translation >=20 > Currently, when using vxlan-gpe or vxlan item in the flow > both are being treated the same with flags 0x8 in vxlan > header. which mean the matching of the item vxlan-gpe > will match any vxlan packet. >=20 > This fix the translation of vxlan gpe item into pmd flow > item. which will by default set the flags to vxlan-gpe > to be 0xc. >=20 > Fixes: 3d694341 ("net/mlx5: add Direct Verbs validation function") > Cc: stable@dpdk.org >=20 > Signed-off-by: Raslan Darawsheh > Acked-by: Matan Azrad matan@mellanox.com > --- > drivers/net/mlx5/mlx5_flow_dv.c | 75 > +++++++++++++++++++++++++++++++++++++++-- > 1 file changed, 73 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/net/mlx5/mlx5_flow_dv.c > b/drivers/net/mlx5/mlx5_flow_dv.c > index d51d17d..2878393 100644 > --- a/drivers/net/mlx5/mlx5_flow_dv.c > +++ b/drivers/net/mlx5/mlx5_flow_dv.c > @@ -5779,6 +5779,76 @@ flow_dv_translate_item_vxlan(void *matcher, > void *key, > } >=20 > /** > + * Add VXLAN-GPE item to matcher and to the value. > + * > + * @param[in, out] matcher > + * Flow matcher. > + * @param[in, out] key > + * Flow matcher value. > + * @param[in] item > + * Flow pattern to translate. > + * @param[in] inner > + * Item is inner pattern. > + */ > + > +static void > +flow_dv_translate_item_vxlan_gpe(void *matcher, void *key, > + const struct rte_flow_item *item, int inner) > +{ > + const struct rte_flow_item_vxlan_gpe *vxlan_m =3D item->mask; > + const struct rte_flow_item_vxlan_gpe *vxlan_v =3D item->spec; > + void *headers_m; > + void *headers_v; > + void *misc_m =3D > + MLX5_ADDR_OF(fte_match_param, matcher, > misc_parameters_3); > + void *misc_v =3D > + MLX5_ADDR_OF(fte_match_param, key, > misc_parameters_3); > + char *vni_m; > + char *vni_v; > + uint16_t dport; > + int size; > + int i; > + uint8_t flags_m =3D 0xff; > + uint8_t flags_v =3D 0xc; > + > + if (inner) { > + headers_m =3D MLX5_ADDR_OF(fte_match_param, matcher, > + inner_headers); > + headers_v =3D MLX5_ADDR_OF(fte_match_param, key, > inner_headers); > + } else { > + headers_m =3D MLX5_ADDR_OF(fte_match_param, matcher, > + outer_headers); > + headers_v =3D MLX5_ADDR_OF(fte_match_param, key, > outer_headers); > + } > + dport =3D item->type =3D=3D RTE_FLOW_ITEM_TYPE_VXLAN ? > + MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE; > + if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) { > + MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, > 0xFFFF); > + MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, > dport); > + } > + if (!vxlan_v) > + return; > + if (!vxlan_m) > + vxlan_m =3D &rte_flow_item_vxlan_gpe_mask; > + size =3D sizeof(vxlan_m->vni); > + vni_m =3D MLX5_ADDR_OF(fte_match_set_misc3, misc_m, > outer_vxlan_gpe_vni); > + vni_v =3D MLX5_ADDR_OF(fte_match_set_misc3, misc_v, > outer_vxlan_gpe_vni); > + memcpy(vni_m, vxlan_m->vni, size); > + for (i =3D 0; i < size; ++i) > + vni_v[i] =3D vni_m[i] & vxlan_v->vni[i]; > + if (vxlan_m->flags) { > + flags_m =3D vxlan_m->flags; > + flags_v =3D vxlan_v->flags; > + } > + MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, > flags_m); > + MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, > flags_v); > + MLX5_SET(fte_match_set_misc3, misc_m, > outer_vxlan_gpe_next_protocol, > + vxlan_m->protocol); > + MLX5_SET(fte_match_set_misc3, misc_v, > outer_vxlan_gpe_next_protocol, > + vxlan_v->protocol); > +} > + > +/** > * Add Geneve item to matcher and to the value. > * > * @param[in, out] matcher > @@ -7559,8 +7629,9 @@ __flow_dv_translate(struct rte_eth_dev *dev, > last_item =3D MLX5_FLOW_LAYER_VXLAN; > break; > case RTE_FLOW_ITEM_TYPE_VXLAN_GPE: > - flow_dv_translate_item_vxlan(match_mask, > match_value, > - items, tunnel); > + flow_dv_translate_item_vxlan_gpe(match_mask, > + match_value, items, > + tunnel); > last_item =3D MLX5_FLOW_LAYER_VXLAN_GPE; > break; > case RTE_FLOW_ITEM_TYPE_GENEVE: > -- > 2.7.4 Patch applied to next-net-mlx, Kindest regards, Raslan Darawsheh