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Thu, 20 Feb 2020 13:23:16 +0000 Received: from AM0PR05MB6707.eurprd05.prod.outlook.com ([fe80::adbd:45ca:54:bba9]) by AM0PR05MB6707.eurprd05.prod.outlook.com ([fe80::adbd:45ca:54:bba9%7]) with mapi id 15.20.2750.016; Thu, 20 Feb 2020 13:23:16 +0000 From: Raslan Darawsheh To: Dekel Peled , Matan Azrad , Slava Ovsiienko CC: "dev@dpdk.org" , "stable@dpdk.org" Thread-Topic: [PATCH v2] net/mlx5: fix match on Ethertype and CVLAN tag Thread-Index: AQHV5+HSGD4Lj4uRrUmE3X1ymG6jqqgkEeyA Date: Thu, 20 Feb 2020 13:23:16 +0000 Message-ID: References: <15d7594cc67448389e09213b2ed13e907c471e3a.1582124890.git.dekelp@mellanox.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=rasland@mellanox.com; x-originating-ip: [212.29.221.74] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: 0f7546d0-6206-4ecf-74d8-08d7b6080b76 x-ms-traffictypediagnostic: AM0PR05MB4467:|AM0PR05MB4467: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:5516; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0f7546d0-6206-4ecf-74d8-08d7b6080b76 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Feb 2020 13:23:16.2837 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 9uyT6bkwzDH6cHJLHhryesaqE5LApsZrVYE5KpIEp/wY1Uz/P+OLZ3iV5Ll3Z9qh2Ytm9ZP5shXMRAUT8J/E7Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR05MB4467 Subject: Re: [dpdk-dev] [PATCH v2] net/mlx5: fix match on Ethertype and CVLAN tag X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi, > -----Original Message----- > From: Dekel Peled > Sent: Thursday, February 20, 2020 1:33 PM > To: Matan Azrad ; Slava Ovsiienko > ; Raslan Darawsheh > Cc: dev@dpdk.org; stable@dpdk.org > Subject: [PATCH v2] net/mlx5: fix match on Ethertype and CVLAN tag >=20 > HW supports match on one Ethertype, the Ethertype following the last > VLAN tag of the packet (see PRM). > Previous patch added specific handling for packets with VLAN tag, > after setting match on Ethertype. >=20 > This patch moves the handling of packets with VLAN tag, to be done > before and instead of setting match on Ethertype. >=20 > Previous patch also added, as part of specific handling for packets > with VLAN tag, the setting of cvlan_tag mask bit in translation of > L3 items. > In case of L3 tunnel there is no inner L2 header, so setting this > mask bit is wrong and causes match failures. >=20 > This patch adds check to make sure L2 header exists before setting > cvlan_tag mask bit for L3 items. >=20 > Fixes: 00f75a40576b ("net/mlx5: fix VLAN match for DV mode") > Cc: stable@dpdk.org >=20 > Signed-off-by: Dekel Peled Tested-by: Raslan Darawsheh > --- > drivers/net/mlx5/mlx5_flow_dv.c | 42 > ++++++++++++++++++++++++++++++++--------- > 1 file changed, 33 insertions(+), 9 deletions(-) >=20 > diff --git a/drivers/net/mlx5/mlx5_flow_dv.c > b/drivers/net/mlx5/mlx5_flow_dv.c > index 467d1ce..6f15a91 100644 > --- a/drivers/net/mlx5/mlx5_flow_dv.c > +++ b/drivers/net/mlx5/mlx5_flow_dv.c > @@ -5213,19 +5213,27 @@ struct field_modify_info modify_tcp[] =3D { > /* The value must be in the range of the mask. */ > for (i =3D 0; i < sizeof(eth_m->dst); ++i) > l24_v[i] =3D eth_m->src.addr_bytes[i] & eth_v- > >src.addr_bytes[i]; > - MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, > - rte_be_to_cpu_16(eth_m->type)); > - l24_v =3D MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, > ethertype); > - *(uint16_t *)(l24_v) =3D eth_m->type & eth_v->type; > if (eth_v->type) { > /* When ethertype is present set mask for tagged VLAN. */ > MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, > 1); > /* Set value for tagged VLAN if ethertype is 802.1Q. */ > if (eth_v->type =3D=3D RTE_BE16(RTE_ETHER_TYPE_VLAN) || > - eth_v->type =3D=3D RTE_BE16(RTE_ETHER_TYPE_QINQ)) > + eth_v->type =3D=3D RTE_BE16(RTE_ETHER_TYPE_QINQ)) { > MLX5_SET(fte_match_set_lyr_2_4, headers_v, > cvlan_tag, > 1); > + /* Return here to avoid setting match on ethertype. > */ > + return; > + } > } > + /* > + * HW supports match on one Ethertype, the Ethertype following the > last > + * VLAN tag of the packet (see PRM). > + * Set match on ethertype only if ETH header is not followed by > VLAN. > + */ > + MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, > + rte_be_to_cpu_16(eth_m->type)); > + l24_v =3D MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, > ethertype); > + *(uint16_t *)(l24_v) =3D eth_m->type & eth_v->type; > } >=20 > /** > @@ -5299,6 +5307,8 @@ struct field_modify_info modify_tcp[] =3D { > * Flow matcher value. > * @param[in] item > * Flow pattern to translate. > + * @param[in] item_flags > + * Bit-fields that holds the items detected until now. > * @param[in] inner > * Item is inner pattern. > * @param[in] group > @@ -5307,6 +5317,7 @@ struct field_modify_info modify_tcp[] =3D { > static void > flow_dv_translate_item_ipv4(void *matcher, void *key, > const struct rte_flow_item *item, > + const uint64_t item_flags, > int inner, uint32_t group) > { > const struct rte_flow_item_ipv4 *ipv4_m =3D item->mask; > @@ -5366,7 +5377,12 @@ struct field_modify_info modify_tcp[] =3D { > ipv4_m->hdr.next_proto_id); > MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, > ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id); > - MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1); > + /* > + * On outer header (which must contains L2), or inner header with L2, > + * set cvlan_tag mask bit to mark this packet as untagged. > + */ > + if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2) > + MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, > 1); > } >=20 > /** > @@ -5378,6 +5394,8 @@ struct field_modify_info modify_tcp[] =3D { > * Flow matcher value. > * @param[in] item > * Flow pattern to translate. > + * @param[in] item_flags > + * Bit-fields that holds the items detected until now. > * @param[in] inner > * Item is inner pattern. > * @param[in] group > @@ -5386,6 +5404,7 @@ struct field_modify_info modify_tcp[] =3D { > static void > flow_dv_translate_item_ipv6(void *matcher, void *key, > const struct rte_flow_item *item, > + const uint64_t item_flags, > int inner, uint32_t group) > { > const struct rte_flow_item_ipv6 *ipv6_m =3D item->mask; > @@ -5471,7 +5490,12 @@ struct field_modify_info modify_tcp[] =3D { > ipv6_m->hdr.proto); > MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, > ipv6_v->hdr.proto & ipv6_m->hdr.proto); > - MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1); > + /* > + * On outer header (which must contains L2), or inner header with L2, > + * set cvlan_tag mask bit to mark this packet as untagged. > + */ > + if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2) > + MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, > 1); > } >=20 > /** > @@ -7574,7 +7598,7 @@ struct field_modify_info modify_tcp[] =3D { > mlx5_flow_tunnel_ip_check(items, next_protocol, > &item_flags, &tunnel); > flow_dv_translate_item_ipv4(match_mask, > match_value, > - items, tunnel, > + items, item_flags, tunnel, > dev_flow->group); > matcher.priority =3D MLX5_PRIORITY_MAP_L3; > last_item =3D tunnel ? > MLX5_FLOW_LAYER_INNER_L3_IPV4 : > @@ -7597,7 +7621,7 @@ struct field_modify_info modify_tcp[] =3D { > mlx5_flow_tunnel_ip_check(items, next_protocol, > &item_flags, &tunnel); > flow_dv_translate_item_ipv6(match_mask, > match_value, > - items, tunnel, > + items, item_flags, tunnel, > dev_flow->group); > matcher.priority =3D MLX5_PRIORITY_MAP_L3; > last_item =3D tunnel ? > MLX5_FLOW_LAYER_INNER_L3_IPV6 : > -- > 1.8.3.1 Patch applied to next-net-mlx, Kindest regards Raslan Darawsheh