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* [dpdk-dev] [PATCH v1] common/mlx5: fix set regex register layout
@ 2020-07-28 17:50 Yuval Avnery
  2020-07-29 15:01 ` Raslan Darawsheh
  0 siblings, 1 reply; 2+ messages in thread
From: Yuval Avnery @ 2020-07-28 17:50 UTC (permalink / raw)
  To: Matan Azrad, Shahaf Shuler, Viacheslav Ovsiienko
  Cc: thomas, dev, yuvalav, orika

Reserved field should be 0x60 instead of 0x40.
Will fail FW check otherwise.

Fixes: be4f4a8b8e3b ("regex/mlx5: add engine status check")
Signed-off-by: Yuval Avnery <yuvalav@mellanox.com>
Acked-by: Ori Kam <orika@mellanox.com>
---
 drivers/common/mlx5/mlx5_prm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 8fab962..c78b462 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -2789,7 +2789,7 @@ struct mlx5_ifc_set_regexp_register_in_bits {
 	u8 engine_id[0x8];
 	u8 register_address[0x20];
 	u8 register_data[0x20];
-	u8 reserved[0x40];
+	u8 reserved[0x60];
 };
 
 struct mlx5_ifc_set_regexp_register_out_bits {
-- 
1.8.3.1


^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [dpdk-dev] [PATCH v1] common/mlx5: fix set regex register layout
  2020-07-28 17:50 [dpdk-dev] [PATCH v1] common/mlx5: fix set regex register layout Yuval Avnery
@ 2020-07-29 15:01 ` Raslan Darawsheh
  0 siblings, 0 replies; 2+ messages in thread
From: Raslan Darawsheh @ 2020-07-29 15:01 UTC (permalink / raw)
  To: Yuval Avnery, Matan Azrad, Shahaf Shuler, Slava Ovsiienko
  Cc: Thomas Monjalon, dev, Yuval Avnery, Ori Kam

Hi,

> -----Original Message-----
> From: dev <dev-bounces@dpdk.org> On Behalf Of Yuval Avnery
> Sent: Tuesday, July 28, 2020 8:51 PM
> To: Matan Azrad <matan@mellanox.com>; Shahaf Shuler
> <shahafs@mellanox.com>; Slava Ovsiienko <viacheslavo@mellanox.com>
> Cc: Thomas Monjalon <thomas@monjalon.net>; dev@dpdk.org; Yuval
> Avnery <yuvalav@mellanox.com>; Ori Kam <orika@mellanox.com>
> Subject: [dpdk-dev] [PATCH v1] common/mlx5: fix set regex register layout
> 
> Reserved field should be 0x60 instead of 0x40.
> Will fail FW check otherwise.
> 
> Fixes: be4f4a8b8e3b ("regex/mlx5: add engine status check")
> Signed-off-by: Yuval Avnery <yuvalav@mellanox.com>
> Acked-by: Ori Kam <orika@mellanox.com>
> ---
>  drivers/common/mlx5/mlx5_prm.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/common/mlx5/mlx5_prm.h
> b/drivers/common/mlx5/mlx5_prm.h
> index 8fab962..c78b462 100644
> --- a/drivers/common/mlx5/mlx5_prm.h
> +++ b/drivers/common/mlx5/mlx5_prm.h
> @@ -2789,7 +2789,7 @@ struct mlx5_ifc_set_regexp_register_in_bits {
>  	u8 engine_id[0x8];
>  	u8 register_address[0x20];
>  	u8 register_data[0x20];
> -	u8 reserved[0x40];
> +	u8 reserved[0x60];
>  };
> 
>  struct mlx5_ifc_set_regexp_register_out_bits {
> --
> 1.8.3.1


Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh

^ permalink raw reply	[flat|nested] 2+ messages in thread

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