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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR08MB4005 Subject: Re: [dpdk-dev] [PATCH v7 2/7] eal: add the APIs to wait until equal X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Konstantin, > -----Original Message----- > From: Ananyev, Konstantin > Sent: Friday, October 18, 2019 12:44 AM > To: Gavin Hu (Arm Technology China) ; > dev@dpdk.org > Cc: nd ; thomas@monjalon.net; > stephen@networkplumber.org; hemant.agrawal@nxp.com; > jerinj@marvell.com; pbhagavatula@marvell.com; Honnappa Nagarahalli > ; Ruifeng Wang (Arm Technology China) > ; Phil Yang (Arm Technology China) > ; Steve Capper > Subject: RE: [dpdk-dev] [PATCH v7 2/7] eal: add the APIs to wait until eq= ual >=20 >=20 > > > > Hi Gavin, > > > > > > > > The rte_wait_until_equal_xx APIs abstract the functionality of > > > 'polling for a memory location to become equal to a given value'. > > > > > > Add the RTE_ARM_USE_WFE configuration entry for aarch64, disabled > > > by default. When it is enabled, the above APIs will call WFE instruct= ion > > > to save CPU cycles and power. > > > > > > Signed-off-by: Gavin Hu > > > Reviewed-by: Ruifeng Wang > > > Reviewed-by: Steve Capper > > > Reviewed-by: Ola Liljedahl > > > Reviewed-by: Honnappa Nagarahalli > > > Reviewed-by: Phil Yang > > > Acked-by: Pavan Nikhilesh > > > --- > > > config/arm/meson.build | 1 + > > > config/common_base | 5 + > > > .../common/include/arch/arm/rte_pause_64.h | 30 ++++++ > > > lib/librte_eal/common/include/generic/rte_pause.h | 106 > +++++++++++++++++++++ > > > 4 files changed, 142 insertions(+) > > > > > > diff --git a/config/arm/meson.build b/config/arm/meson.build > > > index 979018e..b4b4cac 100644 > > > --- a/config/arm/meson.build > > > +++ b/config/arm/meson.build > > > @@ -26,6 +26,7 @@ flags_common_default =3D [ > > > ['RTE_LIBRTE_AVP_PMD', false], > > > > > > ['RTE_SCHED_VECTOR', false], > > > + ['RTE_ARM_USE_WFE', false], > > > ] > > > > > > flags_generic =3D [ > > > diff --git a/config/common_base b/config/common_base > > > index 8ef75c2..8861713 100644 > > > --- a/config/common_base > > > +++ b/config/common_base > > > @@ -111,6 +111,11 @@ CONFIG_RTE_MAX_VFIO_CONTAINERS=3D64 > > > CONFIG_RTE_MALLOC_DEBUG=3Dn > > > CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=3Dn > > > CONFIG_RTE_USE_LIBBSD=3Dn > > > +# Use WFE instructions to implement the rte_wait_for_equal_xxx APIs, > > > +# calling these APIs put the cores in low power state while waiting > > > +# for the memory address to become equal to the expected value. > > > +# This is supported only by aarch64. > > > +CONFIG_RTE_ARM_USE_WFE=3Dn > > > > > > # > > > # Recognize/ignore the AVX/AVX512 CPU flags for performance/power > testing. > > > diff --git a/lib/librte_eal/common/include/arch/arm/rte_pause_64.h > b/lib/librte_eal/common/include/arch/arm/rte_pause_64.h > > > index 93895d3..dabde17 100644 > > > --- a/lib/librte_eal/common/include/arch/arm/rte_pause_64.h > > > +++ b/lib/librte_eal/common/include/arch/arm/rte_pause_64.h > > > @@ -1,5 +1,6 @@ > > > /* SPDX-License-Identifier: BSD-3-Clause > > > * Copyright(c) 2017 Cavium, Inc > > > + * Copyright(c) 2019 Arm Limited > > > */ > > > > > > #ifndef _RTE_PAUSE_ARM64_H_ > > > @@ -17,6 +18,35 @@ static inline void rte_pause(void) > > > asm volatile("yield" ::: "memory"); > > > } > > > > > > +#ifdef RTE_ARM_USE_WFE > > > +#define __WAIT_UNTIL_EQUAL(name, asm_op, wide, type) \ > > > +static __rte_always_inline void \ > > > +rte_wait_until_equal_##name(volatile type * addr, type expected) \ > > > +{ \ > > > + type tmp; \ > > > + asm volatile( \ > > > + #asm_op " %" #wide "[tmp], %[addr]\n" \ > > > + "cmp %" #wide "[tmp], %" #wide "[expected]\n" \ > > > + "b.eq 2f\n" \ > > > + "sevl\n" \ > > > + "1: wfe\n" \ > > > + #asm_op " %" #wide "[tmp], %[addr]\n" \ > > > + "cmp %" #wide "[tmp], %" #wide "[expected]\n" \ > > > + "bne 1b\n" \ > > > + "2:\n" \ > > > + : [tmp] "=3D&r" (tmp) \ > > > + : [addr] "Q"(*addr), [expected] "r"(expected) \ > > > + : "cc", "memory"); \ > > > +} >=20 > One more thought: > Why do you need to write asm code for the whole procedure? > Why not to do like linux kernel: > define wfe() and sev() macros and use them inside normal C code? >=20 > #define sev() asm volatile("sev" : : : "memory") > #define wfe() asm volatile("wfe" : : : "memory") >=20 > Then: > rte_wait_until_equal_32(volatile uint32_t *addr, uint32_t expected, int > memorder) > { > if (__atomic_load_n(addr, memorder) !=3D expected) { > sev(); > do { > wfe(); > } while ((__atomic_load_n(addr, memorder) !=3D expected); > } > } >=20 > ? A really good suggestion, I made corresponding changes to v8 already, but i= t missed a armv8 specific feature after internal discussion. We call wfe to wait/sleep on the 'monitored' address, it will be waken up u= pon someone write to the monitor address, so before wfe, we have to call lo= ad-exclusive instruction to 'monitor'.=20 __atomic_load_n - disassembled to "ldr" does not do so. We have to use "ldx= rh" for relaxed mem ordering and "ldaxrh" for acquire ordering, in example = of 16-bit. Let me re-think coming back to the full assembly procedure or implementing = a 'load-exclusive' function. What do you think?=20 /Gavin > > > +/* Wait for *addr to be updated with expected value */ > > > +__WAIT_UNTIL_EQUAL(relaxed_16, ldxrh, w, uint16_t) > > > +__WAIT_UNTIL_EQUAL(acquire_16, ldaxrh, w, uint16_t) > > > +__WAIT_UNTIL_EQUAL(relaxed_32, ldxr, w, uint32_t) > > > +__WAIT_UNTIL_EQUAL(acquire_32, ldaxr, w, uint32_t) > > > +__WAIT_UNTIL_EQUAL(relaxed_64, ldxr, x, uint64_t) > > > +__WAIT_UNTIL_EQUAL(acquire_64, ldaxr, x, uint64_t) > > > +#endif > > > + > > > #ifdef __cplusplus > > > } > > > #endif > > > diff --git a/lib/librte_eal/common/include/generic/rte_pause.h > b/lib/librte_eal/common/include/generic/rte_pause.h > > > index 52bd4db..8906473 100644 > > > --- a/lib/librte_eal/common/include/generic/rte_pause.h > > > +++ b/lib/librte_eal/common/include/generic/rte_pause.h > > > @@ -1,5 +1,6 @@ > > > /* SPDX-License-Identifier: BSD-3-Clause > > > * Copyright(c) 2017 Cavium, Inc > > > + * Copyright(c) 2019 Arm Limited > > > */ > > > > > > #ifndef _RTE_PAUSE_H_ > > > @@ -12,6 +13,10 @@ > > > * > > > */ > > > > > > +#include > > > +#include > > > +#include > > > + > > > /** > > > * Pause CPU execution for a short while > > > * > > > @@ -20,4 +25,105 @@ > > > */ > > > static inline void rte_pause(void); > > > > > > +/** > > > + * Wait for *addr to be updated with a 16-bit expected value, with a > relaxed > > > + * memory ordering model meaning the loads around this API can be > reordered. > > > + * > > > + * @param addr > > > + * A pointer to the memory location. > > > + * @param expected > > > + * A 16-bit expected value to be in the memory location. > > > + */ > > > +__rte_always_inline > > > +static void > > > +rte_wait_until_equal_relaxed_16(volatile uint16_t *addr, uint16_t > expected); > > > + > > > +/** > > > + * Wait for *addr to be updated with a 32-bit expected value, with a > relaxed > > > + * memory ordering model meaning the loads around this API can be > reordered. > > > + * > > > + * @param addr > > > + * A pointer to the memory location. > > > + * @param expected > > > + * A 32-bit expected value to be in the memory location. > > > + */ > > > +__rte_always_inline > > > +static void > > > +rte_wait_until_equal_relaxed_32(volatile uint32_t *addr, uint32_t > expected); > > > + > > > +/** > > > + * Wait for *addr to be updated with a 64-bit expected value, with a > relaxed > > > + * memory ordering model meaning the loads around this API can be > reordered. > > > + * > > > + * @param addr > > > + * A pointer to the memory location. > > > + * @param expected > > > + * A 64-bit expected value to be in the memory location. > > > + */ > > > +__rte_always_inline > > > +static void > > > +rte_wait_until_equal_relaxed_64(volatile uint64_t *addr, uint64_t > expected); > > > + > > > +/** > > > + * Wait for *addr to be updated with a 16-bit expected value, with a= n > acquire > > > + * memory ordering model meaning the loads after this API can't be > observed > > > + * before this API. > > > + * > > > + * @param addr > > > + * A pointer to the memory location. > > > + * @param expected > > > + * A 16-bit expected value to be in the memory location. > > > + */ > > > +__rte_always_inline > > > +static void > > > +rte_wait_until_equal_acquire_16(volatile uint16_t *addr, uint16_t > expected); > > > + > > > +/** > > > + * Wait for *addr to be updated with a 32-bit expected value, with a= n > acquire > > > + * memory ordering model meaning the loads after this API can't be > observed > > > + * before this API. > > > + * > > > + * @param addr > > > + * A pointer to the memory location. > > > + * @param expected > > > + * A 32-bit expected value to be in the memory location. > > > + */ > > > +__rte_always_inline > > > +static void > > > +rte_wait_until_equal_acquire_32(volatile uint32_t *addr, uint32_t > expected); > > > > LGTM in general. > > One stylish thing: wouldn't it be better to have an API like that: > > rte_wait_until_equal_acquire_X(addr, expected, memory_order) > > ? > > > > I.E. - pass memorder as parameter, not to incorporate it into function > name? > > Less functions, plus user can specify order himself. > > Plus looks similar to C11 atomic instrincts. > > > > > > > + > > > +/** > > > + * Wait for *addr to be updated with a 64-bit expected value, with a= n > acquire > > > + * memory ordering model meaning the loads after this API can't be > observed > > > + * before this API. > > > + * > > > + * @param addr > > > + * A pointer to the memory location. > > > + * @param expected > > > + * A 64-bit expected value to be in the memory location. > > > + */ > > > +__rte_always_inline > > > +static void > > > +rte_wait_until_equal_acquire_64(volatile uint64_t *addr, uint64_t > expected); > > > + > > > +#if !defined(RTE_ARM_USE_WFE) > > > +#define __WAIT_UNTIL_EQUAL(op_name, size, type, memorder) \ > > > +__rte_always_inline \ > > > +static void \ > > > +rte_wait_until_equal_##op_name##_##size(volatile type *addr, \ > > > + type expected) \ > > > +{ \ > > > + while (__atomic_load_n(addr, memorder) !=3D expected) \ > > > + rte_pause(); \ > > > +} > > > + > > > +/* Wait for *addr to be updated with expected value */ > > > +__WAIT_UNTIL_EQUAL(relaxed, 16, uint16_t, __ATOMIC_RELAXED) > > > +__WAIT_UNTIL_EQUAL(acquire, 16, uint16_t, __ATOMIC_ACQUIRE) > > > +__WAIT_UNTIL_EQUAL(relaxed, 32, uint32_t, __ATOMIC_RELAXED) > > > +__WAIT_UNTIL_EQUAL(acquire, 32, uint32_t, __ATOMIC_ACQUIRE) > > > +__WAIT_UNTIL_EQUAL(relaxed, 64, uint64_t, __ATOMIC_RELAXED) > > > +__WAIT_UNTIL_EQUAL(acquire, 64, uint64_t, __ATOMIC_ACQUIRE) > > > +#endif /* RTE_ARM_USE_WFE */ > > > + > > > #endif /* _RTE_PAUSE_H_ */ > > > -- > > > 2.7.4