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Sun, 22 Sep 2019 10:13:37 +0000 Received: from AM4PR05MB3265.eurprd05.prod.outlook.com ([fe80::da9:65ba:1323:a39b]) by AM4PR05MB3265.eurprd05.prod.outlook.com ([fe80::da9:65ba:1323:a39b%7]) with mapi id 15.20.2284.023; Sun, 22 Sep 2019 10:13:37 +0000 From: Slava Ovsiienko To: Matan Azrad , "dev@dpdk.org" CC: Raslan Darawsheh Thread-Topic: [PATCH] net/mlx5: fix transmit doorbell register write barrier Thread-Index: AQHVcRM0Dc55SO36GE+31tZ0JJllQ6c3ePsA Date: Sun, 22 Sep 2019 10:13:37 +0000 Message-ID: References: <1568789674-11264-1-git-send-email-viacheslavo@mellanox.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=viacheslavo@mellanox.com; x-originating-ip: [95.164.10.10] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: a2b67cf1-c507-49cd-99a6-08d73f4588f3 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600167)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020); 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: a2b67cf1-c507-49cd-99a6-08d73f4588f3 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Sep 2019 10:13:37.7554 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: KzpSW2CdLRQCqQfwZbis99hdF7ugkSs2AmfFCKge+IZG8eYyptVv40iov+CMkPTdPn3jk214VvrMPkXqyWSCDxVYYD5GfOSq6F/fa0PrfCk= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR05MB3266 Subject: Re: [dpdk-dev] [PATCH] net/mlx5: fix transmit doorbell register write barrier X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Matan Azrad > Sent: Sunday, September 22, 2019 9:59 > To: Slava Ovsiienko ; dev@dpdk.org > Cc: Raslan Darawsheh > Subject: RE: [PATCH] net/mlx5: fix transmit doorbell register write barri= er >=20 > Hi Slava >=20 > Questions inline. >=20 [.. skipped ...] > > + /* Check the doorbell register mapping type. */ > > + cmd =3D txq_ctrl->uar_mmap_offset / page_size; > > + cmd >>=3D MLX5_UAR_MMAP_CMD_SHIFT; > > + cmd &=3D MLX5_UAR_MMAP_CMD_MASK; > > + if (cmd =3D=3D MLX5_MMAP_GET_NC_PAGES_CMD) > > + txq_ctrl->txq.db_nc =3D 1; >=20 > Are you sure we can't retrieve the value in compile time? It is deduced by rdma_core library in runtime, grounding on the MLX5_SHUT_UP_BF environment variable. This variable is checked by rdma library in ibv device open calls (both verbs/dv). >=20 > > #ifndef RTE_ARCH_64 > > /* Assign an UAR lock according to UAR page number */ > > lock_idx =3D (txq_ctrl->uar_mmap_offset / page_size) & @@ -281,6 > > +289,7 @@ > > uintptr_t uar_va; > > uintptr_t offset; > > const size_t page_size =3D sysconf(_SC_PAGESIZE); > > + unsigned int cmd; > > > > assert(ppriv); > > /* > > @@ -300,6 +309,12 @@ > > } > > addr =3D RTE_PTR_ADD(addr, offset); > > ppriv->uar_table[txq->idx] =3D addr; > > + /* Check the doorbell register mapping type. */ > > + cmd =3D txq_ctrl->uar_mmap_offset / page_size; > > + cmd >>=3D MLX5_UAR_MMAP_CMD_SHIFT; > > + cmd &=3D MLX5_UAR_MMAP_CMD_MASK; > > + if (cmd =3D=3D MLX5_MMAP_GET_NC_PAGES_CMD) > > + txq_ctrl->txq.db_nc =3D 1; >=20 > Looks like double code. > Maybe it is better to get the value by a MACRO? Yes, it would be better. WBR, Slava