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Thu, 5 Sep 2019 12:12:03 +0000 Received: from AM4PR05MB3265.eurprd05.prod.outlook.com ([fe80::da9:65ba:1323:a39b]) by AM4PR05MB3265.eurprd05.prod.outlook.com ([fe80::da9:65ba:1323:a39b%7]) with mapi id 15.20.2220.022; Thu, 5 Sep 2019 12:12:03 +0000 From: Slava Ovsiienko To: Phil Yang , Yongseok Koh , Matan Azrad , =?iso-8859-1?Q?N=E9lio_Laranjeiro?= , "dev@dpdk.org" CC: Thomas Monjalon , "jerinj@marvell.com" , "Honnappa.Nagarahalli@arm.com" , "gavin.hu@arm.com" , "nd@arm.com" , "stable@dpdk.org" Thread-Topic: [PATCH 2/2] net/mlx5: fix Tx CQ doorbell synchronization on aarch64 Thread-Index: AQHVY9h4bf4CU/U3oE66T8cjKZO3GKcc66Lw Date: Thu, 5 Sep 2019 12:12:02 +0000 Message-ID: References: <1567680908-31210-1-git-send-email-phil.yang@arm.com> <1567680908-31210-2-git-send-email-phil.yang@arm.com> In-Reply-To: <1567680908-31210-2-git-send-email-phil.yang@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=viacheslavo@mellanox.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:AM4PR05MB3460; H:AM4PR05MB3265.eurprd05.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: Gxtqov65wbTJxapcfoQfKteUX+wsNLcu1Db0a+CqxwF6k/v/bzPL4LURK7mv5kUdOUKKSsT5OalM6q3HbBNKyXdMjMtgNqwzEPt01oIrIdY+ry5bEdAQTevj1lZKbAYMyY1cpLz/UAU/4YArAVK6B9AsdfKx/lq7DoIRUXDflmqtbf2yLsyPTYAQro55d/IMm+FKuDpvoeIS6hBGIV/CxLnoVEpj2xUgeLf7Kcfr69KaxNnzidKuF6fi0K0NF91h9VYWJBuxkZHK6/7U26b9xkTHANLuv4YAtuUNnL0fnNNMnaKGrkRXh0ng1jC0YbNGaXDLcjMh+5h+XWiMSa96klZe4+2LB4DAWAooTQOiMfy8p/nnZldNqT6JKD6ta0fagR+nJCmqiXt4xHxRSVEKupLteYHmWWI7TAZgTc9DE8I= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5ff934ef-ac86-46fd-1f5d-08d731fa42e5 X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Sep 2019 12:12:02.8492 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: h8Lp3xcaaAlCTeJJhMzm3xIABJ8UiDa+LPUk3Io78U1TIz/HA06mJS9U8CeM7d1hwtpKX/pzhtBqJMUj2/ddK7HSsC+MQ6QlWYUQlxA+nY4= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR05MB3460 Subject: Re: [dpdk-dev] [PATCH 2/2] net/mlx5: fix Tx CQ doorbell synchronization on aarch64 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi, Phil This point is in datapath and performance is very critical. The rte_cio_wmb() may take a lot of CPU cycles, waiting till all previous w= rites become visible for all external (relating to core) agents. The Tx CQE doorbelling = does not need any writes to other locations to be completed, the only concern is not to r= eorder/merge the writes to the same doorbell register of the same sending queue in the t= x_burst() internal sending loop/subsequent calls.=20 As far as I know - the writes to the same location should not be reordered = by any arch (may be merged if memory settings allow this, it is not critical for CQE do= orbell), could you, please, explain why we need explicit hardware fence before CQE d= oorbell update? Do you think doorbell write might be rearranged with previously rea= ds from the ring buffer? WBR, Slava > -----Original Message----- > From: Phil Yang > Sent: Thursday, September 5, 2019 13:55 > To: Yongseok Koh ; Slava Ovsiienko > ; Matan Azrad ; N=E9lio > Laranjeiro ; dev@dpdk.org > Cc: Thomas Monjalon ; jerinj@marvell.com; > Honnappa.Nagarahalli@arm.com; gavin.hu@arm.com; nd@arm.com; > stable@dpdk.org > Subject: [PATCH 2/2] net/mlx5: fix Tx CQ doorbell synchronization on > aarch64 >=20 > For the weaker memory model processors, the compiler barrier is not > sufficient to guarantee the coherent memory update be observed by I/O > device. It needs the coherent I/O memory barrier to enforce the ordering = of > Tx completion queue doorbell operation. >=20 > Fixes: da1df1ccabad ("net/mlx5: fix completion queue drain loop") > Cc: stable@dpdk.org >=20 > Suggested-by: Gavin Hu > Signed-off-by: Phil Yang > Reviewed-by: Gavin Hu > --- > drivers/net/mlx5/mlx5_rxtx.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c > index 4c01187..c11148b 100644 > --- a/drivers/net/mlx5/mlx5_rxtx.c > +++ b/drivers/net/mlx5/mlx5_rxtx.c > @@ -2042,7 +2042,7 @@ mlx5_tx_comp_flush(struct mlx5_txq_data > *restrict txq, > } else { > return; > } > - rte_compiler_barrier(); > + rte_cio_wmb(); > *txq->cq_db =3D rte_cpu_to_be_32(txq->cq_ci); > if (likely(tail !=3D txq->elts_tail)) { > mlx5_tx_free_elts(txq, tail, olx); > -- > 2.7.4