From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id B9DC6A0487 for ; Wed, 3 Jul 2019 08:14:25 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 91547374C; Wed, 3 Jul 2019 08:14:25 +0200 (CEST) Received: from EUR01-DB5-obe.outbound.protection.outlook.com (mail-eopbgr150042.outbound.protection.outlook.com [40.107.15.42]) by dpdk.org (Postfix) with ESMTP id 88FC32B99 for ; Wed, 3 Jul 2019 08:14:24 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Mellanox.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hJoIUSRJnuR+09l0TVLMtjCWeCH9x/u9YZ7BQA+oPQA=; b=WfijcaA4PRex8hsz3r98PS6HRL1itifzredZCjc+HlajdkNqZ949y+djhJol1eKDcL93hTVCYWUXIxTDhaubWgoC9iE5v7R348kGSJCuEDzJ3ykKnms43S2JbvRhLvckd1MHU/Z61B8WdCuCtSqgWCqrgNxdhrMu6GbMfTC2Y7s= Received: from AM4PR05MB3265.eurprd05.prod.outlook.com (10.171.188.154) by AM4PR05MB3507.eurprd05.prod.outlook.com (10.171.190.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2032.20; Wed, 3 Jul 2019 06:14:23 +0000 Received: from AM4PR05MB3265.eurprd05.prod.outlook.com ([fe80::1442:fc4d:41ad:29d2]) by AM4PR05MB3265.eurprd05.prod.outlook.com ([fe80::1442:fc4d:41ad:29d2%5]) with mapi id 15.20.2032.019; Wed, 3 Jul 2019 06:14:23 +0000 From: Slava Ovsiienko To: Jack Min , Raslan Darawsheh , Shahaf Shuler , Yongseok Koh , John McNamara , Marko Kovacevic CC: "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH v2] net/mlx5: support matching on ICMP/ICMP6 Thread-Index: AQHVMJ8T2n4wgF8pskC0Vyn/+h8FvKa4aW/A Date: Wed, 3 Jul 2019 06:14:22 +0000 Message-ID: References: <20190528021456.21611-1-jackmin@mellanox.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=viacheslavo@mellanox.com; x-originating-ip: [95.67.35.250] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 2f7d0fe0-2efc-4b0a-332e-08d6ff7db160 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020); SRVR:AM4PR05MB3507; x-ms-traffictypediagnostic: AM4PR05MB3507: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8882; x-forefront-prvs: 00872B689F x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(4636009)(396003)(136003)(376002)(366004)(39860400002)(346002)(189003)(199004)(13464003)(66066001)(81166006)(33656002)(2906002)(81156014)(14454004)(476003)(11346002)(446003)(486006)(3846002)(30864003)(74316002)(305945005)(14444005)(7736002)(4326008)(86362001)(8936002)(6116002)(66476007)(256004)(8676002)(186003)(53936002)(71200400001)(71190400001)(55016002)(5660300002)(9686003)(6436002)(26005)(229853002)(110136005)(316002)(76176011)(478600001)(25786009)(102836004)(99286004)(53546011)(7696005)(52536014)(68736007)(6246003)(76116006)(66946007)(6506007)(66556008)(66446008)(64756008)(73956011); DIR:OUT; SFP:1101; SCL:1; SRVR:AM4PR05MB3507; H:AM4PR05MB3265.eurprd05.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: NVYJA9MxgsBWbpnTxEbquDP7qPdnvQYvkxhwinlQ1mgj937e4dCB8NLFFLCpf78ICgWrwMYLWhgE1iLlMBd4ZFkorbuSzlDNf5nyXUoQpU4qqRQCf2RMg3hOUxQ2olOKfGp7TlZQrcHzRmoMo7lQTnrUSV4DhFX3+q6rl25mLJQ7tjKwlgNZHXWe4ztA/s/z6yBXquYlQ+HNnQDo/2VHjKqVp/50Lljt1MYqNuBwGP8JeVJ3k5N50Pb4RFh1pnD8gimS7+2foO+NzPeGBHtHfpmPoODva8zq8n3oBaVgHZ6MEWKJH0H+bQtmTuibbS9Xv1tn3SAgn9OXcWZcL4iNZ7i+yxXELVBMYOSYYQMLd51SNrZ8ufHGy5fuTiMHsKbu1YGfjQWXg6unUpqZh+VyqNdN0yaOe7kwKZPWH0W1i4k= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2f7d0fe0-2efc-4b0a-332e-08d6ff7db160 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Jul 2019 06:14:22.9751 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: viacheslavo@mellanox.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR05MB3507 Subject: Re: [dpdk-dev] [PATCH v2] net/mlx5: support matching on ICMP/ICMP6 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi, Xiaoyu Please, see below. With best regards, Slava > -----Original Message----- > From: dev On Behalf Of Xiaoyu Min > Sent: Tuesday, July 2, 2019 9:26 > To: Raslan Darawsheh ; Shahaf Shuler > ; Yongseok Koh ; John > McNamara ; Marko Kovacevic > > Cc: dev@dpdk.org > Subject: [dpdk-dev] [PATCH v2] net/mlx5: support matching on ICMP/ICMP6 >=20 > On DV/DR flow engine, MLX5 can match on ICMP/ICMP6's code and type > field via FLEX Parser, which can be enabled by config FW using FLEX Parse= r > profile 2: >=20 > mlxconfig -d -y set FLEX_PARSER_PROFILE_ENABLE=3D2 What do you thin, would it good to have some example for new item in commit= message? Say, testpmd flow create command with new ICMP/ICMP6 items? >=20 > Signed-off-by: Xiaoyu Min > --- > v2: > * updated release note > --- > doc/guides/nics/mlx5.rst | 15 +++ > doc/guides/rel_notes/release_19_08.rst | 5 + > drivers/net/mlx5/mlx5_flow.c | 102 +++++++++++++++++++++ > drivers/net/mlx5/mlx5_flow.h | 12 +++ > drivers/net/mlx5/mlx5_flow_dv.c | 122 +++++++++++++++++++++++++ > 5 files changed, 256 insertions(+) >=20 > diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index > 4cd6cf88fe..fc63f8712a 100644 > --- a/doc/guides/nics/mlx5.rst > +++ b/doc/guides/nics/mlx5.rst > @@ -160,6 +160,8 @@ Limitations > - can be applied to VF ports only. > - must specify PF port action (packet redirection from VF to PF). >=20 > +- ICMP/ICMP6's code/type matching cannot be supported togeter with IP- > in-IP tunnel. > + > Statistics > ---------- >=20 > @@ -525,6 +527,19 @@ Firmware configuration > IP_OVER_VXLAN_EN True(1) > IP_OVER_VXLAN_PORT >=20 > +- enable ICMP/ICMP6's code/type field matching > + > + .. code-block:: console > + > + mlxconfig -d set FLEX_PARSER_PROFILE_ENABLE=3D2 > + > + Verify configurations are set: > + > + .. code-block:: console > + > + mlxconfig -d query | grep FLEX_PARSER_PROFILE_ENABLE > + FLEX_PARSER_PROFILE_ENABLE 2 > + > Prerequisites > ------------- >=20 > diff --git a/doc/guides/rel_notes/release_19_08.rst > b/doc/guides/rel_notes/release_19_08.rst > index 57364afd8b..0c0c17d7a5 100644 > --- a/doc/guides/rel_notes/release_19_08.rst > +++ b/doc/guides/rel_notes/release_19_08.rst > @@ -126,6 +126,11 @@ New Features > Added telemetry mode to l3fwd-power application to report > application level busyness, empty and full polls of rte_eth_rx_burst()= . >=20 > +* **Updated Mellanox mlx5 driver.** > + > + Updated Mellanox mlx5 driver with new features and improvements, > including: > + > + * Added support for match on ICMP/ICMP6's code and type. >=20 > Removed Items > ------------- > diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c > index cd04c446b5..b730563474 100644 > --- a/drivers/net/mlx5/mlx5_flow.c > +++ b/drivers/net/mlx5/mlx5_flow.c > @@ -1047,6 +1047,108 @@ mlx5_flow_validate_attributes(struct > rte_eth_dev *dev, > return 0; > } >=20 > +/** > + * Validate ICMP6 item. > + * > + * @param[in] item > + * Item specification. > + * @param[in] item_flags > + * Bit-fields that holds the items detected until now. > + * @param[out] error > + * Pointer to error structure. > + * > + * @return > + * 0 on success, a negative errno value otherwise and rte_errno is set= . > + */ > +int > +mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, > + uint64_t item_flags, > + uint8_t target_protocol, > + struct rte_flow_error *error) { > + const struct rte_flow_item_icmp6 *mask =3D item->mask; > + const int tunnel =3D !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); > + const uint64_t l3m =3D tunnel ? MLX5_FLOW_LAYER_INNER_L3 : > + MLX5_FLOW_LAYER_OUTER_L3; > + const uint64_t l4m =3D tunnel ? MLX5_FLOW_LAYER_INNER_L4 : > + MLX5_FLOW_LAYER_OUTER_L4; > + int ret; MLX5_FLOW_LAYER_OUTER_L3 is defined as: MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6 Should we do validation in more strict way and check IPv4 for ICMP, and IPv= 6 for ICMPv6 ? > + > + if (target_protocol !=3D 0xFF && target_protocol !=3D IPPROTO_ICMPV6) > + return rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, > item, > + "protocol filtering not compatible" > + " with ICMP6 layer"); > + if (!(item_flags & l3m)) > + return rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, > item, > + "L3 is mandatory to filter on ICMP"); > + if (item_flags & l4m) > + return rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, > item, > + "multiple L4 layers not supported"); > + if (!mask) > + mask =3D &rte_flow_item_icmp6_mask; > + ret =3D mlx5_flow_item_acceptable > + (item, (const uint8_t *)mask, > + (const uint8_t *)&rte_flow_item_icmp6_mask, > + sizeof(struct rte_flow_item_icmp6), error); > + if (ret < 0) > + return ret; > + return 0; > +} > + > +/** > + * Validate ICMP item. > + * > + * @param[in] item > + * Item specification. > + * @param[in] item_flags > + * Bit-fields that holds the items detected until now. > + * @param[out] error > + * Pointer to error structure. > + * > + * @return > + * 0 on success, a negative errno value otherwise and rte_errno is set= . > + */ > +int > +mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, > + uint64_t item_flags, > + uint8_t target_protocol, > + struct rte_flow_error *error) > +{ > + const struct rte_flow_item_icmp *mask =3D item->mask; > + const int tunnel =3D !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); > + const uint64_t l3m =3D tunnel ? MLX5_FLOW_LAYER_INNER_L3 : > + MLX5_FLOW_LAYER_OUTER_L3; > + const uint64_t l4m =3D tunnel ? MLX5_FLOW_LAYER_INNER_L4 : > + MLX5_FLOW_LAYER_OUTER_L4; > + int ret; > + > + if (target_protocol !=3D 0xFF && target_protocol !=3D IPPROTO_ICMP) > + return rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, > item, > + "protocol filtering not compatible" > + " with ICMP layer"); > + if (!(item_flags & l3m)) > + return rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, > item, > + "L3 is mandatory to filter on ICMP"); > + if (item_flags & l4m) > + return rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, > item, > + "multiple L4 layers not supported"); > + if (!mask) > + mask =3D &rte_flow_item_icmp_mask; > + ret =3D mlx5_flow_item_acceptable > + (item, (const uint8_t *)mask, > + (const uint8_t *)&rte_flow_item_icmp_mask, > + sizeof(struct rte_flow_item_icmp), error); > + if (ret < 0) > + return ret; > + return 0; > +} > + > /** > * Validate Ethernet item. > * > diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h > index 65cfdbda9f..863f5ef720 100644 > --- a/drivers/net/mlx5/mlx5_flow.h > +++ b/drivers/net/mlx5/mlx5_flow.h > @@ -50,6 +50,10 @@ > #define MLX5_FLOW_ITEM_METADATA (1u << 16) #define > MLX5_FLOW_ITEM_PORT_ID (1u << 17) >=20 > +/* Pattern MISC bits. */ > +#define MLX5_FLOW_LAYER_ICMP (1u << 18) #define > MLX5_FLOW_LAYER_ICMP6 > +(1u << 18) > + > /* Outer Masks. */ > #define MLX5_FLOW_LAYER_OUTER_L3 \ > (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | > MLX5_FLOW_LAYER_OUTER_L3_IPV6) @@ -494,5 +498,13 @@ int > mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, > uint64_t item_flags, > struct rte_eth_dev *dev, > struct rte_flow_error *error); > +int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, > + uint64_t item_flags, > + uint8_t target_protocol, > + struct rte_flow_error *error); > +int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, > + uint64_t item_flags, > + uint8_t target_protocol, > + struct rte_flow_error *error); >=20 > #endif /* RTE_PMD_MLX5_FLOW_H_ */ > diff --git a/drivers/net/mlx5/mlx5_flow_dv.c > b/drivers/net/mlx5/mlx5_flow_dv.c index 933ad0b819..6aa79042ea 100644 > --- a/drivers/net/mlx5/mlx5_flow_dv.c > +++ b/drivers/net/mlx5/mlx5_flow_dv.c > @@ -2207,6 +2207,22 @@ flow_dv_validate(struct rte_eth_dev *dev, const > struct rte_flow_attr *attr, > return ret; > last_item =3D MLX5_FLOW_ITEM_METADATA; > break; > + case RTE_FLOW_ITEM_TYPE_ICMP: > + ret =3D mlx5_flow_validate_item_icmp(items, > item_flags, > + next_protocol, > + error); > + if (ret < 0) > + return ret; > + item_flags |=3D MLX5_FLOW_LAYER_ICMP; > + break; > + case RTE_FLOW_ITEM_TYPE_ICMP6: > + ret =3D mlx5_flow_validate_item_icmp6(items, > item_flags, > + next_protocol, > + error); > + if (ret < 0) > + return ret; > + item_flags |=3D MLX5_FLOW_LAYER_ICMP6; > + break; > default: > return rte_flow_error_set(error, ENOTSUP, >=20 > RTE_FLOW_ERROR_TYPE_ITEM, > @@ -3245,6 +3261,102 @@ flow_dv_translate_item_port_id(struct > rte_eth_dev *dev, void *matcher, > return 0; > } >=20 > +/** > + * Add ICMP6 item to matcher and to the value. > + * > + * @param[in, out] matcher > + * Flow matcher. > + * @param[in, out] key > + * Flow matcher value. > + * @param[in] item > + * Flow pattern to translate. > + * @param[in] inner > + * Item is inner pattern. > + */ > +static void > +flow_dv_translate_item_icmp6(void *matcher, void *key, > + const struct rte_flow_item *item, > + int inner) > +{ > + const struct rte_flow_item_icmp6 *icmp6_m =3D item->mask; > + const struct rte_flow_item_icmp6 *icmp6_v =3D item->spec; > + void *headers_m; > + void *headers_v; > + void *misc3_m =3D MLX5_ADDR_OF(fte_match_param, matcher, > + misc_parameters_3); > + void *misc3_v =3D MLX5_ADDR_OF(fte_match_param, key, > misc_parameters_3); > + if (inner) { > + headers_m =3D MLX5_ADDR_OF(fte_match_param, matcher, > + inner_headers); > + headers_v =3D MLX5_ADDR_OF(fte_match_param, key, > inner_headers); > + } else { > + headers_m =3D MLX5_ADDR_OF(fte_match_param, matcher, > + outer_headers); > + headers_v =3D MLX5_ADDR_OF(fte_match_param, key, > outer_headers); > + } > + MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF); > + MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, > IPPROTO_ICMPV6); > + if (!icmp6_v) > + return; > + if (!icmp6_m) > + icmp6_m =3D &rte_flow_item_icmp6_mask; > + MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m- > >type); > + MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type, > + icmp6_v->type & icmp6_m->type); > + MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m- > >code); > + MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code, > + icmp6_v->code & icmp6_m->code); > +} > + > +/** > + * Add ICMP item to matcher and to the value. > + * > + * @param[in, out] matcher > + * Flow matcher. > + * @param[in, out] key > + * Flow matcher value. > + * @param[in] item > + * Flow pattern to translate. > + * @param[in] inner > + * Item is inner pattern. > + */ > +static void > +flow_dv_translate_item_icmp(void *matcher, void *key, > + const struct rte_flow_item *item, > + int inner) > +{ > + const struct rte_flow_item_icmp *icmp_m =3D item->mask; > + const struct rte_flow_item_icmp *icmp_v =3D item->spec; > + void *headers_m; > + void *headers_v; > + void *misc3_m =3D MLX5_ADDR_OF(fte_match_param, matcher, > + misc_parameters_3); > + void *misc3_v =3D MLX5_ADDR_OF(fte_match_param, key, > misc_parameters_3); > + if (inner) { > + headers_m =3D MLX5_ADDR_OF(fte_match_param, matcher, > + inner_headers); > + headers_v =3D MLX5_ADDR_OF(fte_match_param, key, > inner_headers); > + } else { > + headers_m =3D MLX5_ADDR_OF(fte_match_param, matcher, > + outer_headers); > + headers_v =3D MLX5_ADDR_OF(fte_match_param, key, > outer_headers); > + } > + MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF); > + MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, > IPPROTO_ICMP); > + if (!icmp_v) > + return; > + if (!icmp_m) > + icmp_m =3D &rte_flow_item_icmp_mask; > + MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type, > + icmp_m->hdr.icmp_type); > + MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type, > + icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type); > + MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code, > + icmp_m->hdr.icmp_code); > + MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code, > + icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code); } > + > static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] =3D { 0 }; >=20 > #define HEADER_IS_ZERO(match_criteria, headers) > \ > @@ -4020,6 +4132,16 @@ flow_dv_translate(struct rte_eth_dev *dev, > items); > last_item =3D MLX5_FLOW_ITEM_METADATA; > break; > + case RTE_FLOW_ITEM_TYPE_ICMP: > + flow_dv_translate_item_icmp(match_mask, > match_value, > + items, tunnel); > + item_flags |=3D MLX5_FLOW_LAYER_ICMP; > + break; > + case RTE_FLOW_ITEM_TYPE_ICMP6: > + flow_dv_translate_item_icmp6(match_mask, > match_value, > + items, tunnel); > + item_flags |=3D MLX5_FLOW_LAYER_ICMP6; > + break; > default: > break; > } > -- > 2.21.0