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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AM4PR05MB3265.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 50559468-4eba-4652-7d4a-08d823110950 X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Jul 2020 07:32:14.8702 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: RT+UmQXikk6FIJeR/aBhjoVwFvYLNblpOZqwiq3kdmQFaHXznk5YvS2EsxMF1dqjUECHOP4ITFpp8+XR5yKgvM8++xWtN4Y98TQw36mmN5M= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR05MB6084 Subject: Re: [dpdk-dev] [PATCH 04/20] common/mlx5: add mlx5 regex command structs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Acked-by: Viacheslav Ovsiienko > -----Original Message----- > From: Ori Kam > Sent: Sunday, July 5, 2020 12:24 > To: jerinj@marvell.com; xiang.w.wang@intel.com; Matan Azrad > ; Slava Ovsiienko ; > Shahaf Shuler > Cc: guyk@marvell.com; dev@dpdk.org; pbhagavatula@marvell.com; > hemant.agrawal@nxp.com; Opher Reviv ; Alex > Rosenbaum ; dovrat@marvell.com; > pkapoor@marvell.com; nipun.gupta@nxp.com; > bruce.richardson@intel.com; yang.a.hong@intel.com; > harry.chang@intel.com; gu.jian1@zte.com.cn; > shanjiangh@chinatelecom.cn; zhangy.yun@chinatelecom.cn; > lixingfu@huachentel.com; wushuai@inspur.com; yuyingxia@yxlink.com; > fanchenggang@sunyainfo.com; davidfgao@tencent.com; > liuzhong1@chinaunicom.cn; zhaoyong11@huawei.com; oc@yunify.com; > jim@netgate.com; hongjun.ni@intel.com; deri@ntop.org; > fc@napatech.com; arthur.su@lionic.com; Thomas Monjalon > ; Ori Kam ; Raslan > Darawsheh ; Yuval Avnery > > Subject: [PATCH 04/20] common/mlx5: add mlx5 regex command structs >=20 > From: Yuval Avnery >=20 > Add regex commands structs to support regex. >=20 > Signed-off-by: Yuval Avnery > --- > drivers/common/mlx5/mlx5_prm.h | 89 > +++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 88 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/common/mlx5/mlx5_prm.h > b/drivers/common/mlx5/mlx5_prm.h index c2b9a20..ede7810 100644 > --- a/drivers/common/mlx5/mlx5_prm.h > +++ b/drivers/common/mlx5/mlx5_prm.h > @@ -795,7 +795,7 @@ enum { > MLX5_CMD_OP_CREATE_GENERAL_OBJECT =3D 0xa00, > MLX5_CMD_OP_MODIFY_GENERAL_OBJECT =3D 0xa01, > MLX5_CMD_OP_QUERY_GENERAL_OBJECT =3D 0xa02, > - MLX5_CMD_SET_REGEX_PARAM =3D 0xb04, > + MLX5_CMD_SET_REGEX_PARAMS =3D 0xb04, > MLX5_CMD_QUERY_REGEX_PARAMS =3D 0xb05, > MLX5_CMD_SET_REGEX_REGISTERS =3D 0xb06, > MLX5_CMD_QUERY_REGEX_REGISTERS =3D 0xb07, @@ -2526,6 > +2526,93 @@ struct mlx5_ifc_query_qp_in_bits { > u8 reserved_at_60[0x20]; > }; >=20 > +struct regexp_params_field_select_bits { > + u8 reserved_at_0[0x1e]; > + u8 stop_engine[0x1]; > + u8 db_umem_id[0x1]; > +}; > + > +struct mlx5_ifc_regexp_params_bits { > + u8 reserved_at_0[0x1f]; > + u8 stop_engine[0x1]; > + u8 db_umem_id[0x20]; > + u8 db_umem_offset[0x40]; > + u8 reserved_at_80[0x100]; > +}; > + > +struct mlx5_ifc_set_regexp_params_in_bits { > + u8 opcode[0x10]; > + u8 uid[0x10]; > + u8 reserved_at_20[0x10]; > + u8 op_mod[0x10]; > + u8 reserved_at_40[0x18]; > + u8 engine_id[0x8]; > + struct regexp_params_field_select_bits field_select; > + struct mlx5_ifc_regexp_params_bits regexp_params; }; > + > +struct mlx5_ifc_set_regexp_params_out_bits { > + u8 status[0x8]; > + u8 reserved_at_8[0x18]; > + u8 syndrome[0x20]; > + u8 reserved_at_18[0x40]; > +}; > + > +struct mlx5_ifc_query_regexp_params_in_bits { > + u8 opcode[0x10]; > + u8 uid[0x10]; > + u8 reserved_at_20[0x10]; > + u8 op_mod[0x10]; > + u8 reserved_at_40[0x18]; > + u8 engine_id[0x8]; > + u8 reserved[0x20]; > +}; > + > +struct mlx5_ifc_query_regexp_params_out_bits { > + u8 status[0x8]; > + u8 reserved_at_8[0x18]; > + u8 syndrome[0x20]; > + u8 reserved[0x40]; > + struct mlx5_ifc_regexp_params_bits regexp_params; }; > + > +struct mlx5_ifc_set_regexp_register_in_bits { > + u8 opcode[0x10]; > + u8 uid[0x10]; > + u8 reserved_at_20[0x10]; > + u8 op_mod[0x10]; > + u8 reserved_at_40[0x18]; > + u8 engine_id[0x8]; > + u8 register_address[0x20]; > + u8 register_data[0x20]; > + u8 reserved[0x40]; > +}; > + > +struct mlx5_ifc_set_regexp_register_out_bits { > + u8 status[0x8]; > + u8 reserved_at_8[0x18]; > + u8 syndrome[0x20]; > + u8 reserved[0x40]; > +}; > + > +struct mlx5_ifc_query_regexp_register_in_bits { > + u8 opcode[0x10]; > + u8 uid[0x10]; > + u8 reserved_at_20[0x10]; > + u8 op_mod[0x10]; > + u8 reserved_at_40[0x18]; > + u8 engine_id[0x8]; > + u8 register_address[0x20]; > +}; > + > +struct mlx5_ifc_query_regexp_register_out_bits { > + u8 status[0x8]; > + u8 reserved_at_8[0x18]; > + u8 syndrome[0x20]; > + u8 reserved[0x20]; > + u8 register_data[0x20]; > +}; > + > /* CQE format mask. */ > #define MLX5E_CQE_FORMAT_MASK 0xc >=20 > -- > 1.8.3.1