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SFP:1101; SCL:1; SRVR:AM4PR05MB3188; H:AM4PR05MB3265.eurprd05.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: GyjrPpDki+EadrAn6SU6nDwtzfnJlHQVmsDCh3Q1PDhVLQbENMLLsB8TNfINh96pUvpkHQqmcRgmkiKBEAP+p3Ga5W2tkGaGi4CHx3CaR0+O8kzgKbpVezrDo10Rb7cd7VyJuXFvesquEG0nzUH/q4CQF8XZjNAqgAPDebII5kiWOscAsR6UESJkhg2KAGIdSncCygXEOgdb2v+X4cG46ze84yVwDFDIBrSrUTEPoKXb4fjiwKyAK2jCIWklLjoZp0jCmBhk9hLGC4fYR4LHbX39xFsIqxfx9HcOyk4MNxR8i7uka1cTS15vshNAErJ7GnXz8jiYnHT3iXuUoVI3kAakPTbSwTrJzk770Cujvy1VNVzVfkeQP7n1Hsfb9DMMUHmiQHBTXGyPMvh+k+1ROp4VsIMCX0gq11HjqKfX3s0= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: b3dc2f6a-0f50-4460-912c-08d6ff8a90f5 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Jul 2019 07:46:32.1156 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: viacheslavo@mellanox.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR05MB3188 Subject: Re: [dpdk-dev] [Suspected-Phishing][PATCH v3] net/mlx5: support matching on ICMP/ICMP6 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Xiaoyu Min > Sent: Wednesday, July 3, 2019 10:23 > To: Raslan Darawsheh ; Slava Ovsiienko > ; Shahaf Shuler ; > Yongseok Koh ; John McNamara > ; Marko Kovacevic > > Cc: dev@dpdk.org > Subject: [Suspected-Phishing][PATCH v3] net/mlx5: support matching on > ICMP/ICMP6 >=20 > On DV/DR flow engine, MLX5 can match on ICMP/ICMP6's code and type > field via FLEX Parser, which can be enabled by config FW using FLEX Parse= r > profile 2: >=20 > mlxconfig -d -y set FLEX_PARSER_PROFILE_ENABLE=3D2 >=20 > The testpmd commands could be: >=20 > testpmd> flow create 0 ingress pattern eth / ipv4 / > icmp type is 8 code is 0 / end > actions rss queues 0 1 end / end >=20 > testpmd> flow create 0 ingress pattern eth / ipv6 / > icmp6 type is 128 code is 0 / end > actions rss queues 0 1 end / end >=20 > Signed-off-by: Xiaoyu Min Acked-by: Viacheslav Ovsiienko > --- > v2: > * updated release note > v3: > * added example testpmd commands in commit log > * more strictly validation: ICMP needs IPv4; ICMP6 needs IPv6 > --- > doc/guides/nics/mlx5.rst | 15 +++ > doc/guides/rel_notes/release_19_08.rst | 5 + > drivers/net/mlx5/mlx5_flow.c | 104 +++++++++++++++++++++ > drivers/net/mlx5/mlx5_flow.h | 12 +++ > drivers/net/mlx5/mlx5_flow_dv.c | 122 +++++++++++++++++++++++++ > 5 files changed, 258 insertions(+) >=20 > diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index > 4cd6cf88fe..fc63f8712a 100644 > --- a/doc/guides/nics/mlx5.rst > +++ b/doc/guides/nics/mlx5.rst > @@ -160,6 +160,8 @@ Limitations > - can be applied to VF ports only. > - must specify PF port action (packet redirection from VF to PF). >=20 > +- ICMP/ICMP6's code/type matching cannot be supported togeter with IP- > in-IP tunnel. > + > Statistics > ---------- >=20 > @@ -525,6 +527,19 @@ Firmware configuration > IP_OVER_VXLAN_EN True(1) > IP_OVER_VXLAN_PORT >=20 > +- enable ICMP/ICMP6's code/type field matching > + > + .. code-block:: console > + > + mlxconfig -d set FLEX_PARSER_PROFILE_ENABLE=3D2 > + > + Verify configurations are set: > + > + .. code-block:: console > + > + mlxconfig -d query | grep FLEX_PARSER_PROFILE_ENABLE > + FLEX_PARSER_PROFILE_ENABLE 2 > + > Prerequisites > ------------- >=20 > diff --git a/doc/guides/rel_notes/release_19_08.rst > b/doc/guides/rel_notes/release_19_08.rst > index 223479c6d4..52ac20908e 100644 > --- a/doc/guides/rel_notes/release_19_08.rst > +++ b/doc/guides/rel_notes/release_19_08.rst > @@ -128,6 +128,11 @@ New Features > Added telemetry mode to l3fwd-power application to report > application level busyness, empty and full polls of rte_eth_rx_burst()= . >=20 > +* **Updated Mellanox mlx5 driver.** > + > + Updated Mellanox mlx5 driver with new features and improvements, > including: > + > + * Added support for match on ICMP/ICMP6's code and type. >=20 > Removed Items > ------------- > diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c > index dc48252791..534cd9338e 100644 > --- a/drivers/net/mlx5/mlx5_flow.c > +++ b/drivers/net/mlx5/mlx5_flow.c > @@ -1047,6 +1047,110 @@ mlx5_flow_validate_attributes(struct > rte_eth_dev *dev, > return 0; > } >=20 > +/** > + * Validate ICMP6 item. > + * > + * @param[in] item > + * Item specification. > + * @param[in] item_flags > + * Bit-fields that holds the items detected until now. > + * @param[out] error > + * Pointer to error structure. > + * > + * @return > + * 0 on success, a negative errno value otherwise and rte_errno is set= . > + */ > +int > +mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, > + uint64_t item_flags, > + uint8_t target_protocol, > + struct rte_flow_error *error) { > + const struct rte_flow_item_icmp6 *mask =3D item->mask; > + const int tunnel =3D !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); > + const uint64_t l3m =3D tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 : > + MLX5_FLOW_LAYER_OUTER_L3_IPV6; > + const uint64_t l4m =3D tunnel ? MLX5_FLOW_LAYER_INNER_L4 : > + MLX5_FLOW_LAYER_OUTER_L4; > + int ret; > + > + if (target_protocol !=3D 0xFF && target_protocol !=3D IPPROTO_ICMPV6) > + return rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, > item, > + "protocol filtering not compatible" > + " with ICMP6 layer"); > + if (!(item_flags & l3m)) > + return rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, > item, > + "IPv6 is mandatory to filter on" > + " ICMP6"); > + if (item_flags & l4m) > + return rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, > item, > + "multiple L4 layers not supported"); > + if (!mask) > + mask =3D &rte_flow_item_icmp6_mask; > + ret =3D mlx5_flow_item_acceptable > + (item, (const uint8_t *)mask, > + (const uint8_t *)&rte_flow_item_icmp6_mask, > + sizeof(struct rte_flow_item_icmp6), error); > + if (ret < 0) > + return ret; > + return 0; > +} > + > +/** > + * Validate ICMP item. > + * > + * @param[in] item > + * Item specification. > + * @param[in] item_flags > + * Bit-fields that holds the items detected until now. > + * @param[out] error > + * Pointer to error structure. > + * > + * @return > + * 0 on success, a negative errno value otherwise and rte_errno is set= . > + */ > +int > +mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, > + uint64_t item_flags, > + uint8_t target_protocol, > + struct rte_flow_error *error) > +{ > + const struct rte_flow_item_icmp *mask =3D item->mask; > + const int tunnel =3D !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); > + const uint64_t l3m =3D tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 : > + MLX5_FLOW_LAYER_OUTER_L3_IPV4; > + const uint64_t l4m =3D tunnel ? MLX5_FLOW_LAYER_INNER_L4 : > + MLX5_FLOW_LAYER_OUTER_L4; > + int ret; > + > + if (target_protocol !=3D 0xFF && target_protocol !=3D IPPROTO_ICMP) > + return rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, > item, > + "protocol filtering not compatible" > + " with ICMP layer"); > + if (!(item_flags & l3m)) > + return rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, > item, > + "IPv4 is mandatory to filter" > + " on ICMP"); > + if (item_flags & l4m) > + return rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, > item, > + "multiple L4 layers not supported"); > + if (!mask) > + mask =3D &rte_flow_item_icmp_mask; > + ret =3D mlx5_flow_item_acceptable > + (item, (const uint8_t *)mask, > + (const uint8_t *)&rte_flow_item_icmp_mask, > + sizeof(struct rte_flow_item_icmp), error); > + if (ret < 0) > + return ret; > + return 0; > +} > + > /** > * Validate Ethernet item. > * > diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h > index 65cfdbda9f..e44f5050c1 100644 > --- a/drivers/net/mlx5/mlx5_flow.h > +++ b/drivers/net/mlx5/mlx5_flow.h > @@ -50,6 +50,10 @@ > #define MLX5_FLOW_ITEM_METADATA (1u << 16) #define > MLX5_FLOW_ITEM_PORT_ID (1u << 17) >=20 > +/* Pattern MISC bits. */ > +#define MLX5_FLOW_LAYER_ICMP (1u << 18) #define > MLX5_FLOW_LAYER_ICMP6 > +(1u << 19) > + > /* Outer Masks. */ > #define MLX5_FLOW_LAYER_OUTER_L3 \ > (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | > MLX5_FLOW_LAYER_OUTER_L3_IPV6) @@ -494,5 +498,13 @@ int > mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, > uint64_t item_flags, > struct rte_eth_dev *dev, > struct rte_flow_error *error); > +int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, > + uint64_t item_flags, > + uint8_t target_protocol, > + struct rte_flow_error *error); > +int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, > + uint64_t item_flags, > + uint8_t target_protocol, > + struct rte_flow_error *error); >=20 > #endif /* RTE_PMD_MLX5_FLOW_H_ */ > diff --git a/drivers/net/mlx5/mlx5_flow_dv.c > b/drivers/net/mlx5/mlx5_flow_dv.c index 933ad0b819..6aa79042ea 100644 > --- a/drivers/net/mlx5/mlx5_flow_dv.c > +++ b/drivers/net/mlx5/mlx5_flow_dv.c > @@ -2207,6 +2207,22 @@ flow_dv_validate(struct rte_eth_dev *dev, const > struct rte_flow_attr *attr, > return ret; > last_item =3D MLX5_FLOW_ITEM_METADATA; > break; > + case RTE_FLOW_ITEM_TYPE_ICMP: > + ret =3D mlx5_flow_validate_item_icmp(items, > item_flags, > + next_protocol, > + error); > + if (ret < 0) > + return ret; > + item_flags |=3D MLX5_FLOW_LAYER_ICMP; > + break; > + case RTE_FLOW_ITEM_TYPE_ICMP6: > + ret =3D mlx5_flow_validate_item_icmp6(items, > item_flags, > + next_protocol, > + error); > + if (ret < 0) > + return ret; > + item_flags |=3D MLX5_FLOW_LAYER_ICMP6; > + break; > default: > return rte_flow_error_set(error, ENOTSUP, >=20 > RTE_FLOW_ERROR_TYPE_ITEM, > @@ -3245,6 +3261,102 @@ flow_dv_translate_item_port_id(struct > rte_eth_dev *dev, void *matcher, > return 0; > } >=20 > +/** > + * Add ICMP6 item to matcher and to the value. > + * > + * @param[in, out] matcher > + * Flow matcher. > + * @param[in, out] key > + * Flow matcher value. > + * @param[in] item > + * Flow pattern to translate. > + * @param[in] inner > + * Item is inner pattern. > + */ > +static void > +flow_dv_translate_item_icmp6(void *matcher, void *key, > + const struct rte_flow_item *item, > + int inner) > +{ > + const struct rte_flow_item_icmp6 *icmp6_m =3D item->mask; > + const struct rte_flow_item_icmp6 *icmp6_v =3D item->spec; > + void *headers_m; > + void *headers_v; > + void *misc3_m =3D MLX5_ADDR_OF(fte_match_param, matcher, > + misc_parameters_3); > + void *misc3_v =3D MLX5_ADDR_OF(fte_match_param, key, > misc_parameters_3); > + if (inner) { > + headers_m =3D MLX5_ADDR_OF(fte_match_param, matcher, > + inner_headers); > + headers_v =3D MLX5_ADDR_OF(fte_match_param, key, > inner_headers); > + } else { > + headers_m =3D MLX5_ADDR_OF(fte_match_param, matcher, > + outer_headers); > + headers_v =3D MLX5_ADDR_OF(fte_match_param, key, > outer_headers); > + } > + MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF); > + MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, > IPPROTO_ICMPV6); > + if (!icmp6_v) > + return; > + if (!icmp6_m) > + icmp6_m =3D &rte_flow_item_icmp6_mask; > + MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m- > >type); > + MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type, > + icmp6_v->type & icmp6_m->type); > + MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m- > >code); > + MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code, > + icmp6_v->code & icmp6_m->code); > +} > + > +/** > + * Add ICMP item to matcher and to the value. > + * > + * @param[in, out] matcher > + * Flow matcher. > + * @param[in, out] key > + * Flow matcher value. > + * @param[in] item > + * Flow pattern to translate. > + * @param[in] inner > + * Item is inner pattern. > + */ > +static void > +flow_dv_translate_item_icmp(void *matcher, void *key, > + const struct rte_flow_item *item, > + int inner) > +{ > + const struct rte_flow_item_icmp *icmp_m =3D item->mask; > + const struct rte_flow_item_icmp *icmp_v =3D item->spec; > + void *headers_m; > + void *headers_v; > + void *misc3_m =3D MLX5_ADDR_OF(fte_match_param, matcher, > + misc_parameters_3); > + void *misc3_v =3D MLX5_ADDR_OF(fte_match_param, key, > misc_parameters_3); > + if (inner) { > + headers_m =3D MLX5_ADDR_OF(fte_match_param, matcher, > + inner_headers); > + headers_v =3D MLX5_ADDR_OF(fte_match_param, key, > inner_headers); > + } else { > + headers_m =3D MLX5_ADDR_OF(fte_match_param, matcher, > + outer_headers); > + headers_v =3D MLX5_ADDR_OF(fte_match_param, key, > outer_headers); > + } > + MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF); > + MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, > IPPROTO_ICMP); > + if (!icmp_v) > + return; > + if (!icmp_m) > + icmp_m =3D &rte_flow_item_icmp_mask; > + MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type, > + icmp_m->hdr.icmp_type); > + MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type, > + icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type); > + MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code, > + icmp_m->hdr.icmp_code); > + MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code, > + icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code); } > + > static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] =3D { 0 }; >=20 > #define HEADER_IS_ZERO(match_criteria, headers) > \ > @@ -4020,6 +4132,16 @@ flow_dv_translate(struct rte_eth_dev *dev, > items); > last_item =3D MLX5_FLOW_ITEM_METADATA; > break; > + case RTE_FLOW_ITEM_TYPE_ICMP: > + flow_dv_translate_item_icmp(match_mask, > match_value, > + items, tunnel); > + item_flags |=3D MLX5_FLOW_LAYER_ICMP; > + break; > + case RTE_FLOW_ITEM_TYPE_ICMP6: > + flow_dv_translate_item_icmp6(match_mask, > match_value, > + items, tunnel); > + item_flags |=3D MLX5_FLOW_LAYER_ICMP6; > + break; > default: > break; > } > -- > 2.21.0