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DIR:OUT; SFP:1101; SCL:1; SRVR:AM4SPR01MB270; H:AM4PR05MB3425.eurprd05.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 8JOHvT7v58qxEXcm1+Cb5IwMnk8iyQhGoyEA2lO5q+1ehyE+Y/m2FyPG8BZzFNv5TSWh5OVlaMmR3UBMWyc7YQPqwmvb/Yf3go38wPK504jqxsdFPS60kA/ejRyKna4G2xWkrC5WL5BGHAlJvqXPZQTKvXsQ0ARcOryNnuEQJtiLLyk2Zmqjv4yeKf4P3n6r9kpIi3YaUX3okO+Ff50QI/5w02TvCs3AaFtP/cBEkbWk2hl3BTCWHIpNO+Hu7T76i8OHSSwevQO50wRQbUGuSyQ72+PnqcTTHw3r9MCFMz06tDmHOKS3Ck72DHeWoXF0CqAvRr5cpKbzjUMHMyJNlYc3FyVKZyYvAYDqk1s4+d53z9dd0WDyX/AEmQXSEaPkNr1ukW8vl13R3WHX2xbI2HlSNplPVO5gqM++nuqpn9c= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: e88f209a-2146-48a7-5f28-08d714b42061 X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Jul 2019 06:06:56.5106 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: orika@mellanox.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4SPR01MB270 Subject: Re: [dpdk-dev] [RFC,v3] ethdev: extend RSS offload types X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Simei, > -----Original Message----- > From: dev On Behalf Of simei > Sent: Monday, July 29, 2019 5:44 AM > To: qi.z.zhang@intel.com; jingjing.wu@intel.com; ferruh.yigit@intel.com; > Adrien Mazarguil > Cc: dev@dpdk.org; simei.su@intel.com > Subject: [dpdk-dev] [RFC,v3] ethdev: extend RSS offload types >=20 > From: Simei Su >=20 > Make it easier to represent to define macro values as (1ULL << ###). >=20 > This RFC reserves several bits as input set selection from bottom > of the 64 bits. The flow type is combined with input set to > represent rss types. >=20 Why reserve from the bottom? and not from the first available space? > for example: > ETH_RSS_IPV4 | ETH_RSS_INSET_L3_SRC: hash on src ip address only > ETH_RSS_IPV4_UDP | ETH_RSS_INSET_L4_DST: hash on src/dst IP and > dst UDP port > ETH_RSS_L2_PAYLOAD | ETH_RSS_INSET_L2_DST: hash on dst mac address >=20 What happens when the user set ETH_RSS_IPV4? From what I understand from yo= ur RFC this will do nothing since no bits where enabled, am I correct?=20 If I'm correct this may break applications. > Signed-off-by: Simei Su > --- > lib/librte_ethdev/rte_ethdev.h | 13 +++++++++++++ > 1 file changed, 13 insertions(+) >=20 > diff --git a/lib/librte_ethdev/rte_ethdev.h b/lib/librte_ethdev/rte_ethde= v.h > index dc6596b..8af6355 100644 > --- a/lib/librte_ethdev/rte_ethdev.h > +++ b/lib/librte_ethdev/rte_ethdev.h > @@ -508,6 +508,19 @@ struct rte_eth_rss_conf { > #define ETH_RSS_GENEVE (1ULL << RTE_ETH_FLOW_GENEVE) > #define ETH_RSS_NVGRE (1ULL << RTE_ETH_FLOW_NVGRE) >=20 > +/* > + * The following six macros are used combined with ETH_RSS_* to > + * represent rss types. The structure rte_flow_action_rss.types is > + * 64-bit wide and we reserve couple bits here for input set selection > + * from bottom of the 64 bits. > + */ > +#define ETH_RSS_INSET_L2_SRC (1ULL << 63) > +#define ETH_RSS_INSET_L2_DST (1ULL << 62) > +#define ETH_RSS_INSET_L3_SRC (1ULL << 61) > +#define ETH_RSS_INSET_L3_DST (1ULL << 60) > +#define ETH_RSS_INSET_L4_SRC (1ULL << 59) > +#define ETH_RSS_INSET_L4_DST (1ULL << 58) > + > #define ETH_RSS_IP ( \ > ETH_RSS_IPV4 | \ > ETH_RSS_FRAG_IPV4 | \ > -- > 1.8.3.1 Thanks, Ori Kam