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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AM5PR04MB3153.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: facced48-368b-4323-fb8e-08d828e1f2ae X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Jul 2020 17:10:17.6652 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: GUwWbHxxprnzzrLJ0Nl1yEiIVl9ViQ7NrJyk2XRtwVXjDHeMEX3NmCftVp5Yh+722gCHEfQj0xO87+bMOFRwzg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB3973 Subject: Re: [dpdk-dev] [PATCH v2 9/9] crypto/octeontx2: add cryptodev sec dequeue routine X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > From: Vamsi Attunuru >=20 > This patch adds lookaside IPsec dequeue routine. >=20 > Signed-off-by: Vamsi Attunuru > Signed-off-by: Tejasree Kondoj > --- The patch can be squashed into the previous one. As enqueue will not work without dequeue operation. > doc/guides/cryptodevs/octeontx2.rst | 19 ++++++++++ > doc/guides/rel_notes/release_20_08.rst | 5 +++ > drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 37 +++++++++++++++++++ > drivers/crypto/octeontx2/otx2_ipsec_po.h | 30 +++++++++++++++ > 4 files changed, 91 insertions(+) >=20 > diff --git a/doc/guides/cryptodevs/octeontx2.rst > b/doc/guides/cryptodevs/octeontx2.rst > index 085d669e49..5d111e46c3 100644 > --- a/doc/guides/cryptodevs/octeontx2.rst > +++ b/doc/guides/cryptodevs/octeontx2.rst > @@ -158,3 +158,22 @@ application: >=20 > ./test > RTE>>cryptodev_octeontx2_asym_autotest > + > + > +Lookaside IPsec Support > +----------------------- > + > +The OCTEON TX2 SoC can accelerate IPsec traffic in lookaside protocol mo= de, > +with its **cryptographic accelerator (CPT)**. ``OCTEON TX2 crypto PMD`` > implements > +this as an ``RTE_SECURITY_ACTION_TYPE_LOOKASIDE_PROTOCOL`` offload. > + > +Refer to :doc:`../prog_guide/rte_security` for more details on protocol > offloads. > + You can probably add here that the feature can be tested with ipsec-secgw sample application=20 > + > +Features supported > +~~~~~~~~~~~~~~~~~~ > + > +* IPv4 > +* ESP > +* Tunnel mode > +* AES-128/192/256-GCM > diff --git a/doc/guides/rel_notes/release_20_08.rst > b/doc/guides/rel_notes/release_20_08.rst > index f19b748728..2d57adc283 100644 > --- a/doc/guides/rel_notes/release_20_08.rst > +++ b/doc/guides/rel_notes/release_20_08.rst > @@ -225,6 +225,11 @@ New Features > See the :doc:`../sample_app_ug/l2_forward_real_virtual` for more > details of this parameter usage. >=20 > +* **Added lookaside IPsec support to OCTEON TX2 crypto PMD.** > + > + Added lookaside IPsec support to OCTEON TX2 crypto PMD. With this feat= ure, > + applications will be able to offload lookaside IPsec to the hardware. > + Move this bullet as per the order described in this doc(below the new featu= res section). And it would be better to re-phrase the statement as * **Updated the OCTEON TX2 crypto PMD to support rte_security.** Updated the OCTEON TX2 crypto PMD to support ``rte_security`` lookaside protocol offload for IPsec. >=20 > Removed Items > ------------- > diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c > b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c > index 6a2753eb22..9d51b17ddd 100644 > --- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c > +++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c > @@ -835,11 +835,48 @@ otx2_cpt_asym_post_process(struct rte_crypto_op > *cop, > } > } >=20 > + > enum otx2_ipsec_po_comp_e { > OTX2_IPSEC_PO_CC_SUCCESS =3D 0x00, > OTX2_IPSEC_PO_CC_AUTH_UNSUPPORTED =3D 0xB0, > OTX2_IPSEC_PO_CC_ENCRYPT_UNSUPPORTED =3D 0xB1, > + OTX2_IPSEC_PO_CC_IP_VERSION =3D 0xB2, > + OTX2_IPSEC_PO_CC_PROTOCOL =3D 0xB3, > + OTX2_IPSEC_PO_CC_CTX_INVALID =3D 0xB4, > + OTX2_IPSEC_PO_CC_CTX_DIR_MISMATCH =3D 0xB5, > + OTX2_IPSEC_PO_CC_IP_PAYLOAD_TYPE =3D 0xB6, > + OTX2_IPSEC_PO_CC_CTX_FLAG_MISMATCH =3D 0xB7, > + OTX2_IPSEC_PO_CC_GRE_HDR_MISMATCH =3D 0xB8, > + OTX2_IPSEC_PO_CC_GRE_PROTOCOL =3D 0xB9, > + OTX2_IPSEC_PO_CC_CUSTOM_HDR_LEN =3D 0xBA, > + OTX2_IPSEC_PO_CC_ENC_TYPE_CTR_GCM =3D 0xBB, > + OTX2_IPSEC_PO_CC_IPCOMP_CONF =3D 0xBC, > + OTX2_IPSEC_PO_CC_FREG_SIZE_CONF =3D 0xBD, > + OTX2_IPSEC_PO_CC_SPI_MISMATCH =3D 0xBE, > + OTX2_IPSEC_PO_CC_CHECKSUM =3D 0xBF, > + OTX2_IPSEC_PO_CC_IPCOMP_PKT_DETECTED =3D 0xC0, > + OTX2_IPSEC_PO_CC_TFC_PADDING_WITH_PREFRAG =3D 0xC1, > + OTX2_IPSEC_PO_CC_DSIV_INCORRECT_PARAM =3D 0xC2, > + OTX2_IPSEC_PO_CC_AUTH_MISMATCH =3D 0xC3, > + OTX2_IPSEC_PO_CC_PADDING =3D 0xC4, > + OTX2_IPSEC_PO_CC_DUMMY_PADDING =3D 0xC5, > + OTX2_IPSEC_PO_CC_IPV6_EXT_HDRS_TOO_BIG =3D 0xC6, > + OTX2_IPSEC_PO_CC_IPV6_HOP_BY_HOP =3D 0xC7, > + OTX2_IPSEC_PO_CC_IPV6_RH_LENGTH =3D 0xC8, > + OTX2_IPSEC_PO_CC_IPV6_OUTB_RH_COPY_ADDR =3D 0xC9, > + OTX2_IPSEC_PO_CC_IPV6_DEC_RH_SEGS_LEFT =3D 0xCA, > + OTX2_IPSEC_PO_CC_IPV6_HDR_INVALID =3D 0xCB, > + OTX2_IPSEC_PO_CC_IPV6_SELECTOR_MATCH =3D 0xCC, > + OTX2_IPSEC_PO_CC_IPV6_UDP_PAYLOAD_CSUM_MISMATCH =3D 0xCE, > }; Are these error codes? Are they added in the debug prints somewhere? >=20 > enum { > -- > 2.27.0