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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(136003)(396003)(39840400004)(346002)(376002)(36840700001)(46966006)(70586007)(8676002)(82310400003)(33656002)(54906003)(47076005)(53546011)(7696005)(70206006)(6506007)(2906002)(6636002)(110136005)(52536014)(186003)(86362001)(9686003)(478600001)(36860700001)(316002)(83380400001)(55016002)(5660300002)(81166007)(356005)(336012)(8936002)(966005)(26005)(4326008)(21314003); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jul 2021 07:01:10.9010 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 411ef794-ffc2-4a5b-92e1-08d93f82abcb X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT037.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR0801MB1922 Subject: Re: [dpdk-dev] atomic operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Removed invalid mail address. > -----Original Message----- > From: Thomas Monjalon > Sent: Sunday, July 4, 2021 8:38 AM > To: Honnappa Nagarahalli ; Ruifeng Wang > ; Phil Yang > Cc: dev@dpdk.org; bruce.richardson@intel.com; > konstantin.ananyev@intel.com; dev@dpdk.org; > david.marchand@redhat.com; David Christensen > Subject: Re: [dpdk-dev] atomic operations >=20 > 03/07/2021 13:29, Thomas Monjalon: > > In the deprecation notices of DPDK 21.05, we can still read this: > > " > > * rte_atomicNN_xxx: These APIs do not take memory order parameter. > This does > > not allow for writing optimized code for all the CPU architectures > supported > > in DPDK. DPDK will adopt C11 atomic operations semantics and provide > wrappers > > using C11 atomic built-ins. These wrappers must be used for patches t= hat > > need to be merged in 20.08 onwards. This change will not introduce an= y > > performance degradation. > > > > * rte_smp_*mb: These APIs provide full barrier functionality. However, > many > > use cases do not require full barriers. To support such use cases, DP= DK will > > adopt C11 barrier semantics and provide wrappers using C11 atomic bui= lt- > ins. > > These wrappers must be used for patches that need to be merged in > 20.08 > > onwards. This change will not introduce any performance degradation. > > " >=20 > The only new wrapper is rte_atomic_thread_fence(). What else? Yes. The decision was to use GCC atomic built-ins directly.=20 And rte_atomic_thread_fence() is an exception. It is a wrapper of __atomic_= thread_fence(), because mem order __ATOMIC_SEQ_CST has an optimized impleme= ntation for x86. > We are missing clear recommendations. >=20 > > Should we keep these notifications forever? Targeting to obsolete APIs rte_atomicNN_xxx and rte_smp_*mb.=20 Arm is working on replace occurrences with equivalent atomic built-ins. There is still a lot work to do in drivers. > > > > It is very difficult to find which wrapper to use. >=20 > We should make function names explicit instead of "These". >=20 > > This is the guide we have: > > https://doc.dpdk.org/guides/prog_guide/writing_efficient_code.html#loc > > ks-and-atomic-operations > > There are 2 blog posts: > > https://www.dpdk.org/blog/2021/03/26/dpdk-adopts-the-c11-memory- > model/ > > https://www.dpdk.org/blog/2021/06/09/reader-writer-concurrency/ > > > > Basically it says we should use "__atomic builtins" but there is > > example for simple situations like counters, memory barriers, etc. >=20 > Precision: I meant "there is *no* example". >=20 > > Please who could work on improving the documentation? Agree that the documentation needs improve. Add link to list of atomic built-ins and the above mentioned blog posts can= be part of the improvement. >=20 > One simple example: increment a counter atomically. > __atomic_fetch_add(&counter, 1, __ATOMIC_RELAXED); or > __atomic_add_fetch(&counter, 1, __ATOMIC_RELAXED); >=20