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Thu, 17 Jan 2019 15:45:23 +0000 From: Honnappa Nagarahalli To: Gage Eads , "dev@dpdk.org" CC: "olivier.matz@6wind.com" , "arybchenko@solarflare.com" , "bruce.richardson@intel.com" , "konstantin.ananyev@intel.com" , nd , Honnappa Nagarahalli , nd Thread-Topic: [dpdk-dev] [PATCH v3 1/2] eal: add 128-bit cmpset (x86-64 only) Thread-Index: AQHUra7wYmJ+w7UMKEWkA1HXhAc3iqWy9AnA Date: Thu, 17 Jan 2019 15:45:23 +0000 Message-ID: References: <20190115223232.31866-1-gage.eads@intel.com> <20190116151835.22424-1-gage.eads@intel.com> <20190116151835.22424-2-gage.eads@intel.com> In-Reply-To: <20190116151835.22424-2-gage.eads@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Honnappa.Nagarahalli@arm.com; x-originating-ip: [217.140.111.135] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR08MB3095; 6:rYhvD3rOrutiP2UahIQTJryEZNllRzzlUHmdihcxWJnbcqh34nm6c1MnEwtvxZwzrVZELELQ/7oEt75NrpFhIdVuvzri6JxYLxdULJvUYafYDNLB2kADjeRf9DQAPuKj7ngjRn1dhHUfUbvPYlRadAkRHKTpPcAawSG243HmqCR7+swX5Ipvua5/cqZeEeJUN/5TlJ73v6FE1QuSU5bBKCokTn6+U3wJuZ2XLb9m8T4OJCUg/hGBqXZmjK0x7KrFZP90Gp6YGaZ4n+mWebjbXwn8kn/6adUM5rIxkuLzfKAcD3H+td7bAgVgpTwpvMuFiFXqjEOIGOheKFmG7d+Mt5xEdeKkCI5ehlNyhLvf3b1351987vnr8E1PnaoqoAO8DH9y0bq3o2CTaaxYcsWSayuFL4c8c/7hOcEvTPerbKT4jDrYiIMG/eIsblrCc/m3/aViXza9KCoSdkrfTioJKQ==; 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DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR08MB3095; H:AM6PR08MB3672.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: Ywu8KD95uzapp2hIJ+I/v7bcdJacYgM33ZDFfqzi5nrCU+7TsJReS56zlS9PVbbqPsZi9Zn3fh1XrdsGmDny3+pMxfhEyxUkWAEwnxBX8Rhyh83XsIKh1Hvv5lNMxmkh27Y/PY91SczxWLds9hCGbRQV71921RSgCPI62elayqlICrjq0T4ce8OoIS55Os+26tZtI7xicBFKLVZnS+cxzvRTKFfTSuhcUOAxPNFaDyX42B1gGxPEOUXnXoUb4PgvLeauV4fhzmDj/wVlF9l1mD/d0Nxakhd5/n539H5rluT3V14QlzLpmT0WD1S2hnq8WOYeX/s+kcfmbYOdWltbJ70ZkYLgVFMJPRc3M8eeKT91Scfal9ixdO8TwwIFDzLhp8q3ST2ffLfeGrEK6J8oSAyWhAV0JUPIisewWyme+Cs= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1c6d1465-93fd-4127-6e80-08d67c92cb40 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Jan 2019 15:45:23.6090 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR08MB3095 Subject: Re: [dpdk-dev] [PATCH v3 1/2] eal: add 128-bit cmpset (x86-64 only) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Jan 2019 15:45:25 -0000 > Subject: [dpdk-dev] [PATCH v3 1/2] eal: add 128-bit cmpset (x86-64 only) >=20 > This operation can be used for non-blocking algorithms, such as a non- > blocking stack or ring. >=20 > Signed-off-by: Gage Eads > --- > .../common/include/arch/x86/rte_atomic_64.h | 22 > ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) >=20 > diff --git a/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h > b/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h > index fd2ec9c53..34c2addf8 100644 > --- a/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h > +++ b/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h Since this is a 128b operation should there be a new file created with the = name rte_atomic_128.h? > @@ -34,6 +34,7 @@ > /* > * Inspired from FreeBSD src/sys/amd64/include/atomic.h > * Copyright (c) 1998 Doug Rabson > + * Copyright (c) 2019 Intel Corporation > * All rights reserved. > */ >=20 > @@ -208,4 +209,25 @@ static inline void rte_atomic64_clear(rte_atomic64_t > *v) } #endif >=20 > +static inline int > +rte_atomic128_cmpset(volatile uint64_t *dst, uint64_t *exp, uint64_t > +*src) { The API name suggests it is a 128b operation. 'dst', 'exp' and 'src' should= be pointers to 128b (__int128)? Or we could define our own data type. Since, it is a new API, can we define it with memory orderings which will b= e more conducive to relaxed memory ordering based architectures? You can re= fer to [1] and [2] for guidance. If this an external API, it requires 'experimental' tag. 1. https://github.com/ARM-software/progress64/blob/master/src/lockfree/aarc= h64.h#L63 2. https://github.com/ARM-software/progress64/blob/master/src/lockfree/x86-= 64.h#L34 > + uint8_t res; > + > + asm volatile ( > + MPLOCKED > + "cmpxchg16b %[dst];" > + " sete %[res]" > + : [dst] "=3Dm" (*dst), > + [res] "=3Dr" (res) > + : "c" (src[1]), > + "b" (src[0]), > + "m" (*dst), > + "d" (exp[1]), > + "a" (exp[0]) > + : "memory"); > + > + return res; > +} > + > #endif /* _RTE_ATOMIC_X86_64_H_ */ > -- > 2.13.6