From: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
To: "Wang, Yipeng1" <yipeng1.wang@intel.com>,
Jerin Jacob <jerin.jacob@caviumnetworks.com>
Cc: "Richardson, Bruce" <bruce.richardson@intel.com>,
"De Lara Guarch, Pablo" <pablo.de.lara.guarch@intel.com>,
"dev@dpdk.org" <dev@dpdk.org>,
Dharmik Thakkar <Dharmik.Thakkar@arm.com>,
"Gavin Hu (Arm Technology China)" <Gavin.Hu@arm.com>,
nd <nd@arm.com>, "thomas@monjalon.net" <thomas@monjalon.net>,
"Yigit, Ferruh" <ferruh.yigit@intel.com>,
"hemant.agrawal@nxp.com" <hemant.agrawal@nxp.com>,
"chaozhu@linux.vnet.ibm.com" <chaozhu@linux.vnet.ibm.com>,
nd <nd@arm.com>, "Gobriel, Sameh" <sameh.gobriel@intel.com>,
nd <nd@arm.com>
Subject: Re: [dpdk-dev] [PATCH v7 4/5] hash: add lock-free read-write concurrency
Date: Fri, 9 Nov 2018 00:47:55 +0000 [thread overview]
Message-ID: <AM6PR08MB367216A581695E5F512189ED98C60@AM6PR08MB3672.eurprd08.prod.outlook.com> (raw)
In-Reply-To: <D2C4A16CA39F7F4E8E384D204491D7A661514290@ORSMSX105.amr.corp.intel.com>
> >> >
> >> > 9) Does anyone else facing this problem?
> >Any data on x86?
> >
> [Wang, Yipeng]
> I tried Jerin's tests on x86. So by default l3fwd on x86 will use lookup_bulk
> and SIMD instruction so there is no obvious throughput drop on both hit
> and miss cases (for hit case, there is about 2.5% drop though).
Do you mean, if the test case has 'hit only' lookups, there is 2.5% drop?
>
> I manually changed l3fwd to do single packet lookup instead of bulk. For hit
> case there is no throughput drop.
> For miss case, there is 10% throughput drop.
>
> I dig into it, as expected, atomic load indeed translates to regular mov on
> x86.
> But since the reordering of the instruction, the compiler(gcc 5.4) cannot
> unroll the for loop to a switch-case like assembly as before.
> So I believe the reason of performance drops on x86 is because compiler
> cannot optimize the code as well as previously.
Thank you. This makes sense.
> I guess this is totally different reason from why your performance drop on
> non-TSO machine. On non-TSO machine, probably the excessive number of
> atomic load causes a lot of overhead.
>
> A quick fix I found useful on x86 is to read all index together. I am no expert
> on the use of atomic intinsics, but I assume By adding a fence should still
> maintain the correct ordering?
> - uint32_t key_idx;
> + uint32_t key_idx[RTE_HASH_BUCKET_ENTRIES];
> void *pdata;
> struct rte_hash_key *k, *keys = h->key_store;
>
> + memcpy(key_idx, bkt->key_idx, 4 * RTE_HASH_BUCKET_ENTRIES);
> + __atomic_thread_fence(__ATOMIC_ACQUIRE);
> +
> for (i = 0; i < RTE_HASH_BUCKET_ENTRIES; i++) {
> - key_idx = __atomic_load_n(&bkt->key_idx[i],
> - __ATOMIC_ACQUIRE);
> - if (bkt->sig_current[i] == sig && key_idx != EMPTY_SLOT) {
> + if (bkt->sig_current[i] == sig && key_idx[i] !=
> + EMPTY_SLOT){
Thank you for your suggestion. I tried it on Arm platforms, unfortunately it did not help. However, the idea of reducing the number of memory orderings addresses the problem. I worked on a hacked patch for the last couple of days. I have tested it with L3FWD data set, it provides good benefits. I have sent it to you and Jerin. Any feedback will be helpful.
>
> Yipeng
next prev parent reply other threads:[~2018-11-09 0:47 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-26 5:37 [dpdk-dev] [PATCH v7 0/5] Address reader-writer concurrency in rte_hash Honnappa Nagarahalli
2018-10-26 5:37 ` [dpdk-dev] [PATCH v7 1/5] hash: separate multi-writer from rw-concurrency Honnappa Nagarahalli
2018-10-26 5:37 ` [dpdk-dev] [PATCH v7 2/5] hash: support do not free on delete Honnappa Nagarahalli
2018-10-26 5:37 ` [dpdk-dev] [PATCH v7 3/5] hash: fix key store element alignment Honnappa Nagarahalli
2018-10-26 5:37 ` [dpdk-dev] [PATCH v7 4/5] hash: add lock-free read-write concurrency Honnappa Nagarahalli
2018-11-03 11:52 ` Jerin Jacob
2018-11-03 15:40 ` Jerin Jacob
2018-11-06 6:07 ` Honnappa Nagarahalli
2018-11-06 9:10 ` Jerin Jacob
2018-11-06 9:13 ` Thomas Monjalon
2018-11-06 9:47 ` Jerin Jacob
2018-11-09 1:34 ` Honnappa Nagarahalli
2018-11-09 2:20 ` Honnappa Nagarahalli
2018-11-09 9:28 ` Jerin Jacob
2018-11-09 15:37 ` Honnappa Nagarahalli
2018-11-07 2:15 ` Wang, Yipeng1
2018-11-09 0:47 ` Honnappa Nagarahalli [this message]
2018-10-26 5:37 ` [dpdk-dev] [PATCH v7 5/5] test/hash: read-write lock-free concurrency test Honnappa Nagarahalli
2018-10-26 10:52 ` [dpdk-dev] [PATCH v7 0/5] Address reader-writer concurrency in rte_hash Thomas Monjalon
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