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Mon, 4 Mar 2019 20:19:00 +0000 From: Honnappa Nagarahalli To: Gage Eads , "dev@dpdk.org" CC: "olivier.matz@6wind.com" , "arybchenko@solarflare.com" , "bruce.richardson@intel.com" , "konstantin.ananyev@intel.com" , "Gavin Hu (Arm Technology China)" , nd , "chaozhu@linux.vnet.ibm.com" , "jerinj@marvell.com" , "hemant.agrawal@nxp.com" , Honnappa Nagarahalli , nd Thread-Topic: [PATCH v2 1/1] eal: add 128-bit cmpxchg (x86-64 only) Thread-Index: AQHUysXakjH9lmVsC0GbLf2yDq3WuKX797Fw Date: Mon, 4 Mar 2019 20:19:00 +0000 Message-ID: References: <20190128172945.27251-1-gage.eads@intel.com> <20190222154640.22029-1-gage.eads@intel.com> <20190222154640.22029-2-gage.eads@intel.com> In-Reply-To: <20190222154640.22029-2-gage.eads@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Honnappa.Nagarahalli@arm.com; x-originating-ip: [217.140.111.135] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: f66bbf8f-6c6b-477d-049c-08d6a0dea3b0 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR08MB3399; H:AM6PR08MB3672.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: tgED63MJ5Glxdwj/VBGWCHSFALv3hy8O4VZtWwJqko5qLvqWP23IFL48VWzWtuunCxSCqwXpmHtDmKFeLgXLvFDNTaK6ykwA33QxnA0dt5ZQ4bpxjcSrp1pHIvboO//OgPTt4cFYEtF3yOnnanbnCbV7uxkEhIlqyaNeyU8XBIhyTmwHn96DkGjzBPCGmfHIwTG/ZEssqXoEmg4wkMPXVhdDfqCno9PqmEHiq+jyaMOHT0sve9mkvIXKN0XNduDDFo5CZq5vmluuX4ML1CrDRAY1cabDAcE1CH+Wp5L06EenGJWKHjp3b/qaUStXVmAjkbOz5gJ3OwXv1yIP8eHg1cqqZILMQOgykjHEGDudTXI9DfgHU/G3MtV8ylh7T2y01iAL/eO0OMdy3Yb2G1iCnfYPmWeuogP3cQ55aXr0KqQ= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: f66bbf8f-6c6b-477d-049c-08d6a0dea3b0 X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Mar 2019 20:19:00.7368 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR08MB3399 Subject: Re: [dpdk-dev] [PATCH v2 1/1] eal: add 128-bit cmpxchg (x86-64 only) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 04 Mar 2019 20:19:03 -0000 > This operation can be used for non-blocking algorithms, such as a non-blo= cking > stack or ring. >=20 > Signed-off-by: Gage Eads > --- > .../common/include/arch/x86/rte_atomic_64.h | 33 ++++++++++++ > lib/librte_eal/common/include/generic/rte_atomic.h | 59 > ++++++++++++++++++++++ > 2 files changed, 92 insertions(+) >=20 > diff --git a/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h > b/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h > index fd2ec9c53..413e5361b 100644 > --- a/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h > +++ b/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h > @@ -34,6 +34,7 @@ > /* > * Inspired from FreeBSD src/sys/amd64/include/atomic.h > * Copyright (c) 1998 Doug Rabson > + * Copyright (c) 2019 Intel Corporation > * All rights reserved. > */ >=20 > @@ -46,6 +47,7 @@ >=20 > #include > #include > +#include > #include >=20 > /*------------------------- 64 bit atomic operations -------------------= ------*/ @@ - > 208,4 +210,35 @@ static inline void rte_atomic64_clear(rte_atomic64_t *v)= } > #endif >=20 > +static inline int __rte_experimental > +rte_atomic128_cmpxchg(rte_int128_t *dst, > + rte_int128_t *exp, > + const rte_int128_t *src, > + unsigned int weak, > + int success, > + int failure) > +{ > + RTE_SET_USED(weak); > + RTE_SET_USED(success); > + RTE_SET_USED(failure); > + uint8_t res; > + > + asm volatile ( > + MPLOCKED > + "cmpxchg16b %[dst];" > + " sete %[res]" > + : [dst] "=3Dm" (dst->val[0]), > + "=3Da" (exp->val[0]), > + "=3Dd" (exp->val[1]), > + [res] "=3Dr" (res) > + : "b" (src->val[0]), > + "c" (src->val[1]), > + "a" (exp->val[0]), > + "d" (exp->val[1]), > + "m" (dst->val[0]) > + : "memory"); > + > + return res; > +} > + > #endif /* _RTE_ATOMIC_X86_64_H_ */ > diff --git a/lib/librte_eal/common/include/generic/rte_atomic.h > b/lib/librte_eal/common/include/generic/rte_atomic.h > index 4afd1acc3..7c43896e9 100644 > --- a/lib/librte_eal/common/include/generic/rte_atomic.h > +++ b/lib/librte_eal/common/include/generic/rte_atomic.h > @@ -14,6 +14,7 @@ >=20 > #include > #include > +#include >=20 > #ifdef __DOXYGEN__ >=20 > @@ -1082,4 +1083,62 @@ static inline void > rte_atomic64_clear(rte_atomic64_t *v) } #endif >=20 > +/*------------------------ 128 bit atomic operations > +-------------------------*/ > + > +#if defined(RTE_ARCH_X86_64) > +/** > + * 128-bit integer structure. > + */ > +RTE_STD_C11 > +typedef struct { > + RTE_STD_C11 > + union { > + uint64_t val[2]; > + __int128 int128; > + }; > +} __rte_aligned(16) rte_int128_t; > + > +/** > + * An atomic compare and set function used by the mutex functions. > + * (Atomically) Equivalent to: > + * if (*dst =3D=3D exp) Should be, "if (*dst =3D=3D *exp)" > + * *dst =3D src Should be "*dst =3D *src" > + * else > + * *exp =3D *dst > + * > + * @note The success and failure arguments must be one of the > +__ATOMIC_* values > + * defined in the C++11 standard. For details on their behavior, refer > +to the > + * standard. > + * > + * @param dst > + * The destination into which the value will be written. > + * @param exp > + * Pointer to the expected value. If the operation fails, this memory = is > + * updated with the actual value. > + * @param src > + * Pointer to the new value. > + * @param weak > + * A value of true allows the comparison to spuriously fail and allows= the > + * 'exp' update to occur non-atomically (i.e. a torn read may occur). > + * Implementations may ignore this argument and only implement the str= ong > + * variant. > + * @param success > + * If successful, the operation's memory behavior conforms to this (or= a > + * stronger) model. > + * @param failure > + * If unsuccessful, the operation's memory behavior conforms to this (= or a > + * stronger) model. This argument cannot be __ATOMIC_RELEASE, > + * __ATOMIC_ACQ_REL, or a stronger model than success. > + * @return > + * Non-zero on success; 0 on failure. > + */ > +static inline int __rte_experimental > +rte_atomic128_cmpxchg(rte_int128_t *dst, Name could be more neutral. May be rte_atomic128_compare/cmp_exchange? > + rte_int128_t *exp, > + const rte_int128_t *src, > + unsigned int weak, > + int success, > + int failure); > +#endif > + > #endif /* _RTE_ATOMIC_H_ */ > -- > 2.13.6 Few minor comments. I have not reviewed the x86 implementation. Otherwise, Reviewed-by: Honnappa Nagarahalli