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Sat, 3 Nov 2018 09:34:36 +0000 From: Honnappa Nagarahalli To: "Gavin Hu (Arm Technology China)" , Bruce Richardson CC: "dev@dpdk.org" , "thomas@monjalon.net" , "stephen@networkplumber.org" , "olivier.matz@6wind.com" , "chaozhu@linux.vnet.ibm.com" , "konstantin.ananyev@intel.com" , "jerin.jacob@caviumnetworks.com" , "stable@dpdk.org" , nd Thread-Topic: [PATCH v5 2/2] ring: move the atomic load of head above the loop Thread-Index: AQHUcp49OfgaJynQ0UyoxekcYFcYwKU8XWEAgADj64CAAIZUcA== Date: Sat, 3 Nov 2018 09:34:36 +0000 Message-ID: References: <1541066031-29125-1-git-send-email-gavin.hu@arm.com> <1541157688-40012-3-git-send-email-gavin.hu@arm.com> <20181102114344.GA13324@bricha3-MOBL.ger.corp.intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Honnappa.Nagarahalli@arm.com; x-originating-ip: [217.140.111.135] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; 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DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR08MB3032; H:AM6PR08MB3672.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: fYLpF/tutMaxYcsLRBJf/wpvowOkAdorGH47v9qZfqKT7AGxuIiKL0SQVBl7XRXjLMmtANGpcMqU3xl/116GAdWwgxB/dfEoRkpbpd6Y4E2JGEboBnuSw2cBxXGLt8koVo5vwSxlYBBiX8SN1tpbENGMOtCoeE0hC6CeSxZ29kloFXiG3zkAUnS/I8JruNfDXM4/RRJBRKkzh/NNykBXVla2wtN4rYdFST+Io+/RoqO9xT9c9daBB12Q2J7Dn08ui+alB+xN3igX4QziTX0oNsyJ48XtApYXO/SAxcvuouyarwDsVz0yuZmk8gGiX+kMkBJafljpotktHvYQ8POjz8fnVNnOqFDbt+19OFhRXkI= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: eebdb108-df00-4b70-726e-08d6416f9234 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Nov 2018 09:34:36.8879 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR08MB3032 Subject: Re: [dpdk-dev] [PATCH v5 2/2] ring: move the atomic load of head above the loop X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 03 Nov 2018 09:34:38 -0000 > > > --- > > > doc/guides/rel_notes/release_18_11.rst | 7 +++++++ > > > lib/librte_ring/rte_ring_c11_mem.h | 10 ++++------ > > > 2 files changed, 11 insertions(+), 6 deletions(-) > > > > > > diff --git a/doc/guides/rel_notes/release_18_11.rst > > > b/doc/guides/rel_notes/release_18_11.rst > > > index 376128f..b68afab 100644 > > > --- a/doc/guides/rel_notes/release_18_11.rst > > > +++ b/doc/guides/rel_notes/release_18_11.rst > > > @@ -69,6 +69,13 @@ New Features > > > checked out against that dma mask and rejected if out of range. > > > If more > > than > > > one device has addressing limitations, the dma mask is the more > > restricted one. > > > > > > +* **Updated the ring library with C11 memory model.** > > > + > > > + Updated the ring library with C11 memory model, in our tests the > > > + changes decreased latency by 27~29% and 3~15% for MPMC and SPSC > > cases respectively. > > > + The real improvements may vary with the number of contending > > > + lcores and the size of ring. > > > + > > Is this a little misleading, and will users expect massive performance > > improvements generally? The C11 model seems to be used only on some, > > but not all, arm platforms, and then only with "make" builds. > > > > config/arm/meson.build: ['RTE_USE_C11_MEM_MODEL', false]] This is an error. There is already an agreement that on Arm based platforms= , C11 memory model would be used by default. Specific platforms can overrid= e it if required. Would this be ab acceptable change for RC2 or RC3? > > config/common_armv8a_linuxapp:CONFIG_RTE_USE_C11_MEM_MODEL=3Dy > > config/common_base:CONFIG_RTE_USE_C11_MEM_MODEL=3Dn > > config/defconfig_arm64-thunderx-linuxapp- > > gcc:CONFIG_RTE_USE_C11_MEM_MODEL=3Dn > > > > /Bruce >=20 > Thank you Bruce for the review, to limit the scope of improvement, I rewr= ite > the note as follows, could you help review? Feel free to change anything = if you > like. > " Updated the ring library with C11 memory model, running > ring_perf_autotest on Cavium ThunderX2 platform, the changes decreased > latency by 27~29% and 3~15% for MPMC and SPSC cases (2 lcores) > respectively. Note the changes help the relaxed memory ordering > architectures (arm, ppc) only when CONFIG_RTE_USE_C11_MEM_MODEL=3Dy > was configured, no impact on strong memory ordering architectures like x8= 6. > To what extent they help the real use cases depends on other factors, lik= e the > number of contending readers/writers, size of the ring, whether or not it= is on > the critical path." >=20 > /Gavin IMO, mentioning the performance numbers requires mentioning system configur= ations. I suggest we keep this somewhat vague (which will make the users to= run the test on their specific platform) and simple. Can I suggest the fol= lowing: "C11 memory model algorithm for ring library is updated. This results in im= proved performance on some Arm based platforms."