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Mon, 5 Nov 2018 21:51:42 +0000 From: Honnappa Nagarahalli To: =?iso-8859-1?Q?Mattias_R=F6nnblom?= , Thomas Monjalon , Jerin Jacob CC: "Gavin Hu (Arm Technology China)" , "dev@dpdk.org" , "stable@dpdk.org" , Ola Liljedahl , "olivier.matz@6wind.com" , "chaozhu@linux.vnet.ibm.com" , "bruce.richardson@intel.com" , "konstantin.ananyev@intel.com" , nd Thread-Topic: [dpdk-dev] [PATCH 1/2] ring: synchronize the load and store of the tail Thread-Index: AQHUbgeZgXYg3h5Zpk+L4BhhMKuRSaU+hBlwgAMX72A= Date: Mon, 5 Nov 2018 21:51:42 +0000 Message-ID: References: <1537172244-64874-2-git-send-email-gavin.hu@arm.com> <1874944.OrACW1nkDZ@xps> <20181027150024.GA2294@jerin> <17713879.gC9jYcxDUo@xps> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Honnappa.Nagarahalli@arm.com; x-originating-ip: [217.140.111.135] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR08MB3095; 6:thxyQpdcFS4yxjSGxz74Pr0zp+0d8DuTfK1krCWBttJ1mznEkXrmD+tOyQLso4E6EOWh0Gsjo12RR1Pak4qpzUBmUi3AgUunpKA57R7ClzvaU2gP6iG4ahKp5UiVSdzAE7sGrzCK/izPjUmAZbrV30WmkHJRbc1vvyFjtNcP7HeUwULxGCE673S7NOov8NYVCHikX1STiC2qOgOMlkqf0O306jSdtT35xH6DItiOurRDPkH/F96JyuL0slFQKr/V4OhHJ2D59fhfoUSWbNOgEBAvG9aahzbjXqLtuKpeDVUSpP1YaxrTjLifctiT2F9xAcFKTMkFsgNA6JxbmQh8lc6mA/540Nu+yFju/2iVh2W/6ixKN4DhNGQzby4vNKW5e0cuArh+DVlkoM4AdSnRxBW3nHp0+gmv/EGycYlBKv59p8+hdkhuV+jzobMy7gidvlDOrk6XWrEPyHUg+Lo6Eg==; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: d40869dd-709b-47fd-f56e-08d64368df91 X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Nov 2018 21:51:42.5227 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR08MB3095 Subject: Re: [dpdk-dev] [PATCH 1/2] ring: synchronize the load and store of the tail X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 05 Nov 2018 21:51:44 -0000 > > > > 27/10/2018 17:00, Jerin Jacob: > > > From: Thomas Monjalon > > > > The thread is totally messed up because: > > > > - there is no cover letter > > > > - some different series (testpmd, i40e and doc) are in the > > > > same > > thread > > > > - v4 replies to a different series > > > > - this version should be a v5 but has no number > > > > - this version replies to the v3 > > > > - patchwork still shows v3 and "v5" > > > > - replies from Ola are not quoting previous discussion > > > > > > > > Because of all of this, it is really difficult to follow. > > > > This is probably the reason of the lack of review outside of Arm. > > > > > > > > One more issue: you must Cc the relevant maintainers. > > > > Here: > > > > - Olivier for rte_ring > > > > - Chao for IBM platform > > > > - Bruce and Konstantin for x86 > > > > > > > > Guys, it is really cool to have more Arm developpers in DPDK. > > > > But please consider better formatting your discussions, it is > > > > really important in our contribution workflow. > > > > > > > > I don't know what to do. > > > > I suggest to wait for more feedbacks and integrate it in -rc2. > > > > > > This series has been acked and tested. Sure, if we are looking for > > > some more feedback we can push to -rc2 if not it a good candidate to > > > be selected for -rc1. > > > > It has been acked and tested only for Arm platforms. > > And Olivier, the ring maintainer, was not Cc. > > > > I feel it is not enough. > > >=20 > I've just run an out-of-tree test program I have for the DSW scheduler, w= hich > verify scheduler atomic semantics. The results are: > Non-C11 mode: pass > C11 mode before this patch set: fail > C11 mode after this patch set: pass >=20 > This suggests the current C11 mode is broken even on x86_64. I haven't > been following this thread closely, so maybe this is known already. >=20 > I've also run an out-of-tree DSW throughput benchmark, and I've found tha= t > going from Non-C11 to C11 gives a 4% slowdown. After this patch, the > slowdown is only 2,8%. This is interesting. The general understanding seems to be that C11 atomics= should not add any additional instructions on x86. But, we still see some = drop in performance. Is this attributed to compiler not being allowed to re= -order? >=20 > GCC 7.3.0 and a Skylake x86_64.