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Thu, 31 Jan 2019 05:48:14 +0000 From: Honnappa Nagarahalli To: Gage Eads , "dev@dpdk.org" CC: "olivier.matz@6wind.com" , "arybchenko@solarflare.com" , "bruce.richardson@intel.com" , "konstantin.ananyev@intel.com" , "Gavin Hu (Arm Technology China)" , nd , "chaozhu@linux.vnet.ibm.com" , "jerinj@marvell.com" , "hemant.agrawal@nxp.com" , nd Thread-Topic: [PATCH 1/1] eal: add 128-bit cmpset (x86-64 only) Thread-Index: AQHUty75k/HjXbn82Ey1zVpEls/JgKXI2b8A Date: Thu, 31 Jan 2019 05:48:14 +0000 Message-ID: References: <20190128172945.27251-1-gage.eads@intel.com> <20190128172945.27251-2-gage.eads@intel.com> In-Reply-To: <20190128172945.27251-2-gage.eads@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Honnappa.Nagarahalli@arm.com; x-originating-ip: [217.140.111.135] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM6PR08MB3575; 6:zpsR8UxITaWzli7Q7dkf7rbQe//RLEr4cB4asw5QuyOoNHyeo4FCKQl/+dgWMVwNVV5G5rGPrRV8mR59HvftQ3zmdWZMBI98YsB3RmmB+/3lRJzU4sp8H+5xdJLdZO9jgxc22HcmgYtZ9yFe/igJKcI+jdrsf66WayB1nOkeblGLG+i7o2VaYg9nTbg02pB624UUGvE1EQNyQ5UbfPisTCt6Em3I/jQE8tI8eqat+W21ONOdsRNvGEZuLxOH+VQRfbBhdt210maa4fgp4vj2yKVi8gSmkrzw3Pw1wal/au0XAQJUiAN2ytVcn+uhMV5FVIbj9zVi5OoCsDqW8D0MKrFV/1cNbKX0LdTjQQTnclUgn/1261X056W0mjB98V1nFLXbEeTNKiS1dJabhdSX6Rm4LXx4bo/VPiTk+lBphQLX5YaBcWC/QW04pY7656FTaOX3l6Knuf/M6h3M/cqTrQ==; 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DIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR08MB3575; H:AM6PR08MB3672.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: GdnUtC5hCmzJGIGGdChkxc9tdfGu+NrnjIjEf0Q10EW7pxclZRWi2di4mT1b379l59DG2zBx1Zq+w2AJNdkfNj6UDxw6fInDiSXCTAF96UoXKnqhRYy5Hhh4FqqsAf/UTSgH/i+0YjiHwgXls7Ao0rjbe0LQTkx54cifQYHGXW0/UZf5vecdbA8zcz0Rmyv/79wFc55zmt0N78pk7mCBNjiFLXHq+K+teeKVnIJdEX43+66C8unn6NhrZ46PrrslJGCtdngOSVivPshHxY+iT+MuVvwyrRO0/WBymbwXvt86YXbYhbkBWd+oqwbZI4L6gGm4mLjrITezwCa9aVKTqwrdnJy9WinzLnGOMwOkKHlZBV3KwkkZDsXZYGdrgjqR6XWMhaDdN1H/1urpJBRAsPdbeAnXBWzSNLM7m2fGpIM= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4033c103-7a12-402a-df8f-08d6873fb137 X-MS-Exchange-CrossTenant-originalarrivaltime: 31 Jan 2019 05:48:14.4801 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR08MB3575 Subject: Re: [dpdk-dev] [PATCH 1/1] eal: add 128-bit cmpset (x86-64 only) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 Jan 2019 05:48:17 -0000 >=20 > This operation can be used for non-blocking algorithms, such as a non- > blocking stack or ring. >=20 > Signed-off-by: Gage Eads > --- > .../common/include/arch/x86/rte_atomic_64.h | 31 +++++++++++ > lib/librte_eal/common/include/generic/rte_atomic.h | 65 > ++++++++++++++++++++++ > 2 files changed, 96 insertions(+) >=20 > diff --git a/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h > b/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h > index fd2ec9c53..b7b90b83e 100644 > --- a/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h > +++ b/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h > @@ -34,6 +34,7 @@ > /* > * Inspired from FreeBSD src/sys/amd64/include/atomic.h > * Copyright (c) 1998 Doug Rabson > + * Copyright (c) 2019 Intel Corporation > * All rights reserved. > */ >=20 > @@ -46,6 +47,7 @@ >=20 > #include > #include > +#include > #include >=20 > /*------------------------- 64 bit atomic operations -------------------= ------*/ @@ - > 208,4 +210,33 @@ static inline void rte_atomic64_clear(rte_atomic64_t *v)= } > #endif >=20 > +static inline int __rte_experimental > +rte_atomic128_cmpset(volatile rte_int128_t *dst, Does it make sense to call is rte_atomic128_compare_exchange (or ..._cmp_xc= hg) to indicate it is a compare-exchange operation? > + rte_int128_t *exp, rte_int128_t *src, > + unsigned int weak, > + enum rte_atomic_memmodel_t success, > + enum rte_atomic_memmodel_t failure) { > + RTE_SET_USED(weak); > + RTE_SET_USED(success); > + RTE_SET_USED(failure); > + uint8_t res; > + > + asm volatile ( > + MPLOCKED > + "cmpxchg16b %[dst];" > + " sete %[res]" > + : [dst] "=3Dm" (dst->val[0]), > + "=3DA" (exp->val[0]), > + [res] "=3Dr" (res) > + : "c" (src->val[1]), > + "b" (src->val[0]), > + "m" (dst->val[0]), > + "d" (exp->val[1]), > + "a" (exp->val[0]) > + : "memory"); > + > + return res; > +} > + > #endif /* _RTE_ATOMIC_X86_64_H_ */ > diff --git a/lib/librte_eal/common/include/generic/rte_atomic.h > b/lib/librte_eal/common/include/generic/rte_atomic.h > index b99ba4688..8d612d566 100644 > --- a/lib/librte_eal/common/include/generic/rte_atomic.h > +++ b/lib/librte_eal/common/include/generic/rte_atomic.h > @@ -14,6 +14,7 @@ >=20 > #include > #include > +#include >=20 > #ifdef __DOXYGEN__ >=20 > @@ -1082,4 +1083,68 @@ static inline void > rte_atomic64_clear(rte_atomic64_t *v) } #endif >=20 > +/*------------------------ 128 bit atomic operations > +-------------------------*/ > + > +/** > + * 128-bit integer structure. > + */ > +typedef struct { > + uint64_t val[2]; > +} __rte_aligned(16) rte_int128_t; It looks like '__int128' is available from gcc 4.6. I think we should use '= __int128'. We can have it as an internal structure for ease of programming. > + > +/** > + * Memory consistency models used in atomic operations. These control > +the > + * behavior of the operation with respect to memory barriers and > + * thread synchronization. > + * > + * These directly match those in the C++11 standard; for details on > +their > + * behavior, refer to the standard. > + */ > +enum rte_atomic_memmodel_t { > + RTE_ATOMIC_RELAXED, > + RTE_ATOMIC_CONSUME, > + RTE_ATOMIC_ACQUIRE, > + RTE_ATOMIC_RELEASE, > + RTE_ATOMIC_ACQ_REL, > + RTE_ATOMIC_SEQ_CST, > +}; IMO, we can use the GCC provided names. I do not see any advantage to defin= ing our own. > + > +/* Only implemented on x86-64 currently. The ifdef prevents compilation > +from > + * failing for architectures without a definition of this function. > + */ Minor comment. We can skip the above comments, the #if below is pretty obvi= ous. > +#if defined(RTE_ARCH_X86_64) > +/** > + * An atomic compare and set function used by the mutex functions. > + * (atomic) equivalent to: > + * if (*dst =3D=3D exp) > + * *dst =3D src (all 128-bit words) > + * > + * @param dst > + * The destination into which the value will be written. > + * @param exp > + * Pointer to the expected value. If the operation fails, this memory = is > + * updated with the actual value. > + * @param src > + * Pointer to the new value. > + * @param weak > + * A value of true allows the comparison to spuriously fail. > Implementations > + * may ignore this argument and only implement the strong variant. > + * @param success > + * If successful, the operation's memory behavior conforms to this (or= a > + * stronger) model. > + * @param failure > + * If unsuccessful, the operation's memory behavior conforms to this (= or a > + * stronger) model. This argument cannot be RTE_ATOMIC_RELEASE, > + * RTE_ATOMIC_ACQ_REL, or a stronger model than success. > + * @return > + * Non-zero on success; 0 on failure. > + */ > +static inline int __rte_experimental > +rte_atomic128_cmpset(volatile rte_int128_t *dst, > + rte_int128_t *exp, rte_int128_t *src, > + unsigned int weak, > + enum rte_atomic_memmodel_t success, > + enum rte_atomic_memmodel_t failure); #endif > + > #endif /* _RTE_ATOMIC_H_ */ > -- > 2.13.6