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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(52536014)(33656002)(7696005)(81166007)(8676002)(2906002)(8936002)(336012)(86362001)(83380400001)(4326008)(5660300002)(70586007)(47076005)(54906003)(508600001)(316002)(82310400003)(356005)(186003)(53546011)(9686003)(6506007)(36860700001)(55016002)(6862004)(26005)(70206006); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jul 2021 07:19:27.1457 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 586be56d-b25f-4255-e943-08d952613319 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT059.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR08MB6414 Subject: Re: [dpdk-dev] [PATCH v3 4/8] test/mcslock: use compiler atomics for lcores sync X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Olivier, > -----Original Message----- > From: Olivier Matz > Sent: Wednesday, July 28, 2021 5:57 PM > To: Joyce Kong > Cc: thomas@monjalon.net; david.marchand@redhat.com; > roretzla@linux.microsoft.com; stephen@networkplumber.org; > andrew.rybchenko@oktetlabs.ru; harry.van.haaren@intel.com; Honnappa > Nagarahalli ; Ruifeng Wang > ; dev@dpdk.org; nd > Subject: Re: [PATCH v3 4/8] test/mcslock: use compiler atomics for lcores > sync >=20 > Hi Joyce, >=20 > On Mon, Jul 19, 2021 at 10:51:21PM -0500, Joyce Kong wrote: > > Convert rte_atomic usages to compiler atomic built-ins for lcores sync > > in mcslock testcases. > > > > Signed-off-by: Joyce Kong > > Reviewed-by: Ruifeng Wang > > Acked-by: Stephen Hemminger > > --- > > app/test/test_mcslock.c | 14 ++++++-------- > > 1 file changed, 6 insertions(+), 8 deletions(-) > > > > diff --git a/app/test/test_mcslock.c b/app/test/test_mcslock.c index > > 80eaecc90a..52e45e7e2a 100644 > > --- a/app/test/test_mcslock.c > > +++ b/app/test/test_mcslock.c > > @@ -17,7 +17,6 @@ > > #include > > #include > > #include > > -#include > > > > #include "test.h" > > > > @@ -43,7 +42,7 @@ rte_mcslock_t *p_ml_perf; > > > > static unsigned int count; > > > > -static rte_atomic32_t synchro; > > +static uint32_t synchro; > > > > static int > > test_mcslock_per_core(__rte_unused void *arg) @@ -76,8 +75,7 @@ > > load_loop_fn(void *func_param) > > rte_mcslock_t ml_perf_me; > > > > /* wait synchro */ > > - while (rte_atomic32_read(&synchro) =3D=3D 0) > > - ; > > + rte_wait_until_equal_32(&synchro, 1, __ATOMIC_RELAXED); > > > > begin =3D rte_get_timer_cycles(); > > while (lcount < MAX_LOOP) { > > @@ -102,15 +100,15 @@ test_mcslock_perf(void) > > const unsigned int lcore =3D rte_lcore_id(); > > > > printf("\nTest with no lock on single core...\n"); > > - rte_atomic32_set(&synchro, 1); > > + __atomic_store_n(&synchro, 1, __ATOMIC_RELAXED); > > load_loop_fn(&lock); > > printf("Core [%u] Cost Time =3D %"PRIu64" us\n", > > lcore, time_count[lcore]); > > memset(time_count, 0, sizeof(time_count)); > > > > printf("\nTest with lock on single core...\n"); > > + __atomic_store_n(&synchro, 1, __ATOMIC_RELAXED); > > lock =3D 1; > > - rte_atomic32_set(&synchro, 1); >=20 > nit: is there a reason for moving this line? I meant to use __atomic_store_n() instead of rte_atomic32_set() to set sync= hro, but put the operation to the line up 'lock=3D1' by mistake, will change it. > >=20 > > load_loop_fn(&lock); > > printf("Core [%u] Cost Time =3D %"PRIu64" us\n", > > lcore, time_count[lcore]); > > @@ -118,11 +116,11 @@ test_mcslock_perf(void) > > > > printf("\nTest with lock on %u cores...\n", (rte_lcore_count())); > > > > - rte_atomic32_set(&synchro, 0); > > + __atomic_store_n(&synchro, 0, __ATOMIC_RELAXED); > > rte_eal_mp_remote_launch(load_loop_fn, &lock, SKIP_MAIN); > > > > /* start synchro and launch test on main */ > > - rte_atomic32_set(&synchro, 1); > > + __atomic_store_n(&synchro, 1, __ATOMIC_RELAXED); > > load_loop_fn(&lock); >=20 > I have a more general question. Please forgive my ignorance about the > C++11 atomic builtins and memory model. Both gcc manual and C11 > standard > are not that easy to understand :) >=20 > In all the patches of this patchset, __ATOMIC_RELAXED is used. My > understanding is that it does not add any inter-thread ordering constrain= t. I > suppose that in this particular case, we rely on the call to > rte_eal_mp_remote_launch() being a compiler barrier, and the function its= elf > to be a memory barrier. This ensures that worker threads sees synchro=3D0 > until it is set to 1 by the master. > Is it correct? >=20 Yes, you are right. __ATOMIC_RELAXED would introduce no barrier, and the wo= rker threads would sync with master thread by 'synchro'. > What is the reason for using the atomic API here? Wouldn't a standard > affectation work too? (I mean "synchro =3D 1;") >=20 Here, __atomic_store_n(__ATOMIC_RELAXED) is used to ensure worker threads see 'synchro=3D1' after it is changed by the master. And a standard affecti= on can not ensure worker threads get the new value. >=20 > > > > rte_eal_mp_wait_lcore(); > > -- > > 2.17.1 > >